summaryrefslogtreecommitdiff
path: root/frontends/ast
Commit message (Expand)AuthorAge
* Fixed memory->start_offset handlingClifford Wolf2015-01-01
* Added global yosys_celltypesClifford Wolf2014-12-29
* dict/pool changes in astClifford Wolf2014-12-29
* Changed more code to dict<> and pool<>Clifford Wolf2014-12-28
* Fixed mem2reg warning messageClifford Wolf2014-12-27
* Added Yosys::{dict,nodict,vector} container typesClifford Wolf2014-12-26
* Renamed extend() to extend_xx(), changed most users to extend_u0()Clifford Wolf2014-12-24
* Added log_warning() APIClifford Wolf2014-11-09
* AST simplifier: optimize constant AST_CASE nodes before recursively descendingClifford Wolf2014-10-29
* Improvements in $readmem[bh] implementationClifford Wolf2014-10-26
* Added support for $readmemh/$readmembClifford Wolf2014-10-26
* Fixed constant "cond ? string1 : string2" with strings of different sizeClifford Wolf2014-10-25
* minor indenting correctionsClifford Wolf2014-10-19
* Builds on Mac 10.9.2 with LLVM 3.5.Parviz Palangpour2014-10-19
* Fixed various VS warningsClifford Wolf2014-10-18
* Wrapped math in int constructorWilliam Speirs2014-10-17
* Fixed handling of invalid array access in mem2reg codeClifford Wolf2014-10-16
* Do not the 'z' modifier in format string (another win32 fix)Clifford Wolf2014-10-11
* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-10
* namespace YosysClifford Wolf2014-09-27
* Another $clog2 bugfixClifford Wolf2014-09-08
* Fixed $clog2 (off by one error)Clifford Wolf2014-09-06
* Fixed assignment of out-of bounds array elementClifford Wolf2014-09-06
* Corrected spelling mistakes found by lintianRuben Undheim2014-09-06
* Removed $bu0 cell typeClifford Wolf2014-09-04
* Added emscripten (emcc) support to build system and some build fixesClifford Wolf2014-08-22
* Archibald Rust and Clifford Wolf: ffi-based dpi_call()Clifford Wolf2014-08-22
* Fixed small memory leak in ast simplifyClifford Wolf2014-08-21
* Added support for DPI function with different names in C and VerilogClifford Wolf2014-08-21
* Added AstNode::asInt()Clifford Wolf2014-08-21
* Fixed memory leak in DPI function callsClifford Wolf2014-08-21
* Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)Clifford Wolf2014-08-21
* Added support for global tasks and functionsClifford Wolf2014-08-21
* Added "via_celltype" attribute on task/funcClifford Wolf2014-08-18
* Added const folding of AST_CASE to AST simplifierClifford Wolf2014-08-18
* Improved AST ProcessGenerator performanceClifford Wolf2014-08-17
* Use stackmap<> in AST ProcessGeneratorClifford Wolf2014-08-17
* AST ProcessGenerator: replaced subst_*_{from,to} with subst_*_mapClifford Wolf2014-08-16
* Fixed bug in "read_verilog -ignore_redef"Clifford Wolf2014-08-15
* Added RTLIL::SigSpec::to_sigbit_map()Clifford Wolf2014-08-14
* Changed the AST genWidthRTLIL subst interface to use a std::mapClifford Wolf2014-08-14
* Fixed handling of task outputsClifford Wolf2014-08-14
* Added module->portsClifford Wolf2014-08-14
* Added AST_MULTIRANGE (arrays with more than 1 dimension)Clifford Wolf2014-08-06
* Improved scope resolution of local regs in Verilog+AST frontendClifford Wolf2014-08-05
* Fixed AST handling of variables declared inside a functions main blockClifford Wolf2014-08-05
* More bugfixes related to new RTLIL::IdStringClifford Wolf2014-08-02
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-02
* Preparations for RTLIL::IdString redesign: cleanup of existing codeClifford Wolf2014-08-02
* Replaced sha1 implementationClifford Wolf2014-08-01