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* New upstream version 0.9Ruben Undheim2019-10-18
* Imported GIT HEAD: 0.8+20190328git32bd0f2Ruben Undheim2019-03-28
* New upstream version 0.7+20180830git0b7a184Ruben Undheim2018-08-30
* Imported yosys 0.7Ruben Undheim2016-11-03
* Squashed commit of the following:Ruben Undheim2016-09-23
* Fixed oom bug in ilang parserClifford Wolf2015-11-29
* Fixed performance bug in ilang parserClifford Wolf2015-11-27
* Import more std:: stuff into Yosys namespaceClifford Wolf2015-10-25
* Adjust makefiles to work with out-of-tree buildsClifford Wolf2015-08-12
* Fixed trailing whitespacesClifford Wolf2015-07-02
* Enable bison to be customizedFabio Utzig2015-01-08
* Fixed memory->start_offset handlingClifford Wolf2015-01-01
* Added Yosys::{dict,nodict,vector} container typesClifford Wolf2014-12-26
* Re-introduced Yosys::readsome() helper functionClifford Wolf2014-10-23
* Updated .gitignore file for ilang and verilog frontendsClifford Wolf2014-10-15
* Updated lexers & parsers to include prefixesWilliam Speirs2014-10-15
* Fixed win32 troubles with f.readsome()Clifford Wolf2014-10-11
* namespace YosysClifford Wolf2014-09-27
* Changed frontend-api from FILE to std::istreamClifford Wolf2014-08-23
* Added module->portsClifford Wolf2014-08-14
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-31
* Added module->design and cell->module, wire->module pointersClifford Wolf2014-07-31
* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-31
* Added wire->upto flag for signals such as "wire [0:7] x;"Clifford Wolf2014-07-28
* Fixed ilang parser for new RTLIL APIClifford Wolf2014-07-27
* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-26
* Added RTLIL::Cell::has(portname)Clifford Wolf2014-07-26
* Manual fixes for new cell connections APIClifford Wolf2014-07-26
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-25
* Added "make PRETTY=1"Clifford Wolf2014-07-24
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3Clifford Wolf2014-07-23
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3Clifford Wolf2014-07-23
* SigSpec refactoring: change RTLIL::SigSpec::size() to be read-onlyClifford Wolf2014-07-22
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
* Fixed ilang parsing of process attributesClifford Wolf2014-07-22
* Fixed make rules for ilang parserClifford Wolf2014-07-22
* Added "autoidx" statement to ilang file formatClifford Wolf2014-07-21
* Fixed clang -Wdeprecated-register warningsClifford Wolf2014-04-20
* Replaced depricated %name-prefix= bison directiveClifford Wolf2014-04-20
* Bugfix in ilang frontend autoidx recoveryClifford Wolf2014-03-07
* renamed ilang "scope error" to "ilang error"Clifford Wolf2014-02-11
* Improved ilang parser error messagesClifford Wolf2014-02-09
* Fixed comment/eol parsing in ilang frontendClifford Wolf2014-02-01
* Added updating of RTLIL::autoidx to ilang frontendClifford Wolf2014-01-03
* Replaced signed_parameters API with CONST_FLAG_SIGNEDClifford Wolf2013-12-04
* Added support for signed parameters in ilangClifford Wolf2013-11-24
* Remove auto_wire framework (smarter than the verilog standard)Clifford Wolf2013-11-24