yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	Clifford Wolf	2014-07-23
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3	Clifford Wolf	2014-07-23
*	SigSpec refactoring: change RTLIL::SigSpec::size() to be read-only	Clifford Wolf	2014-07-22
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22
*	Fixed ilang parsing of process attributes	Clifford Wolf	2014-07-22
*	Added "autoidx" statement to ilang file format	Clifford Wolf	2014-07-21
*	Replaced depricated %name-prefix= bison directive	Clifford Wolf	2014-04-20
*	renamed ilang "scope error" to "ilang error"	Clifford Wolf	2014-02-11
*	Improved ilang parser error messages	Clifford Wolf	2014-02-09
*	Fixed comment/eol parsing in ilang frontend	Clifford Wolf	2014-02-01
*	Replaced signed_parameters API with CONST_FLAG_SIGNED	Clifford Wolf	2013-12-04
*	Added support for signed parameters in ilang	Clifford Wolf	2013-11-24
*	Remove auto_wire framework (smarter than the verilog standard)	Clifford Wolf	2013-11-24
*	Major improvements in mem2reg and added "init" sync rules	Clifford Wolf	2013-11-21
*	Fixed ilang parser: memory width	Clifford Wolf	2013-11-20
*	Fixed memory leak in ilang frontend	Clifford Wolf	2013-05-23
*	initial import	Clifford Wolf	2013-01-05