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path: root/frontends/ilang/parser.y
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* Added module->design and cell->module, wire->module pointersClifford Wolf2014-07-31
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* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-31
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* Added wire->upto flag for signals such as "wire [0:7] x;"Clifford Wolf2014-07-28
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* Fixed ilang parser for new RTLIL APIClifford Wolf2014-07-27
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* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-26
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* Added RTLIL::Cell::has(portname)Clifford Wolf2014-07-26
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* Manual fixes for new cell connections APIClifford Wolf2014-07-26
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* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
| | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;'
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
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* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-25
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* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3Clifford Wolf2014-07-23
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* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3Clifford Wolf2014-07-23
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* SigSpec refactoring: change RTLIL::SigSpec::size() to be read-onlyClifford Wolf2014-07-22
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* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
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* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
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* Fixed ilang parsing of process attributesClifford Wolf2014-07-22
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* Added "autoidx" statement to ilang file formatClifford Wolf2014-07-21
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* Replaced depricated %name-prefix= bison directiveClifford Wolf2014-04-20
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* renamed ilang "scope error" to "ilang error"Clifford Wolf2014-02-11
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* Improved ilang parser error messagesClifford Wolf2014-02-09
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* Fixed comment/eol parsing in ilang frontendClifford Wolf2014-02-01
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* Replaced signed_parameters API with CONST_FLAG_SIGNEDClifford Wolf2013-12-04
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* Added support for signed parameters in ilangClifford Wolf2013-11-24
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* Remove auto_wire framework (smarter than the verilog standard)Clifford Wolf2013-11-24
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* Major improvements in mem2reg and added "init" sync rulesClifford Wolf2013-11-21
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* Fixed ilang parser: memory widthClifford Wolf2013-11-20
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* Fixed memory leak in ilang frontendClifford Wolf2013-05-23
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* initial importClifford Wolf2013-01-05