index
:
yosys
master
Debian dgit repo for package yosys
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
frontends
/
ilang
Commit message (
Expand
)
Author
Age
*
New upstream version 0.9
Ruben Undheim
2019-10-18
*
Imported GIT HEAD: 0.8+20190328git32bd0f2
Ruben Undheim
2019-03-28
*
New upstream version 0.7+20180830git0b7a184
Ruben Undheim
2018-08-30
*
Imported yosys 0.7
Ruben Undheim
2016-11-03
*
Squashed commit of the following:
Ruben Undheim
2016-09-23
*
Fixed oom bug in ilang parser
Clifford Wolf
2015-11-29
*
Fixed performance bug in ilang parser
Clifford Wolf
2015-11-27
*
Import more std:: stuff into Yosys namespace
Clifford Wolf
2015-10-25
*
Adjust makefiles to work with out-of-tree builds
Clifford Wolf
2015-08-12
*
Fixed trailing whitespaces
Clifford Wolf
2015-07-02
*
Enable bison to be customized
Fabio Utzig
2015-01-08
*
Fixed memory->start_offset handling
Clifford Wolf
2015-01-01
*
Added Yosys::{dict,nodict,vector} container types
Clifford Wolf
2014-12-26
*
Re-introduced Yosys::readsome() helper function
Clifford Wolf
2014-10-23
*
Updated .gitignore file for ilang and verilog frontends
Clifford Wolf
2014-10-15
*
Updated lexers & parsers to include prefixes
William Speirs
2014-10-15
*
Fixed win32 troubles with f.readsome()
Clifford Wolf
2014-10-11
*
namespace Yosys
Clifford Wolf
2014-09-27
*
Changed frontend-api from FILE to std::istream
Clifford Wolf
2014-08-23
*
Added module->ports
Clifford Wolf
2014-08-14
*
Renamed port access function on RTLIL::Cell, added param access functions
Clifford Wolf
2014-07-31
*
Added module->design and cell->module, wire->module pointers
Clifford Wolf
2014-07-31
*
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
Clifford Wolf
2014-07-31
*
Added wire->upto flag for signals such as "wire [0:7] x;"
Clifford Wolf
2014-07-28
*
Fixed ilang parser for new RTLIL API
Clifford Wolf
2014-07-27
*
Changed a lot of code to the new RTLIL::Wire constructors
Clifford Wolf
2014-07-26
*
Added RTLIL::Cell::has(portname)
Clifford Wolf
2014-07-26
*
Manual fixes for new cell connections API
Clifford Wolf
2014-07-26
*
Changed users of cell->connections_ to the new API (sed command)
Clifford Wolf
2014-07-26
*
Renamed RTLIL::{Module,Cell}::connections to connections_
Clifford Wolf
2014-07-26
*
Use only module->addCell() and module->remove() to create and delete cells
Clifford Wolf
2014-07-25
*
Added "make PRETTY=1"
Clifford Wolf
2014-07-24
*
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3
Clifford Wolf
2014-07-23
*
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3
Clifford Wolf
2014-07-23
*
SigSpec refactoring: change RTLIL::SigSpec::size() to be read-only
Clifford Wolf
2014-07-22
*
SigSpec refactoring: using the accessor functions everywhere
Clifford Wolf
2014-07-22
*
SigSpec refactoring: renamed chunks and width to __chunks and __width
Clifford Wolf
2014-07-22
*
Fixed ilang parsing of process attributes
Clifford Wolf
2014-07-22
*
Fixed make rules for ilang parser
Clifford Wolf
2014-07-22
*
Added "autoidx" statement to ilang file format
Clifford Wolf
2014-07-21
*
Fixed clang -Wdeprecated-register warnings
Clifford Wolf
2014-04-20
*
Replaced depricated %name-prefix= bison directive
Clifford Wolf
2014-04-20
*
Bugfix in ilang frontend autoidx recovery
Clifford Wolf
2014-03-07
*
renamed ilang "scope error" to "ilang error"
Clifford Wolf
2014-02-11
*
Improved ilang parser error messages
Clifford Wolf
2014-02-09
*
Fixed comment/eol parsing in ilang frontend
Clifford Wolf
2014-02-01
*
Added updating of RTLIL::autoidx to ilang frontend
Clifford Wolf
2014-01-03
*
Replaced signed_parameters API with CONST_FLAG_SIGNED
Clifford Wolf
2013-12-04
*
Added support for signed parameters in ilang
Clifford Wolf
2013-11-24
*
Remove auto_wire framework (smarter than the verilog standard)
Clifford Wolf
2013-11-24
[next]