path: root/frontends/verilog/
Commit message (Expand)AuthorAge
* Added warning for use of 'z' constants in HDLClifford Wolf2014-11-14
* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-31
* Using log_assert() instead of assert()Clifford Wolf2014-07-28
* Improved parsing of large integer constantsClifford Wolf2014-06-15
* Fixed handling of unsized constants in verilog frontendClifford Wolf2014-01-24
* Major redesign of expr width/sign detecion (verilog/ast frontend)Clifford Wolf2013-07-09
* Added SAT generator and simple sat_solve commandClifford Wolf2013-06-07
* initial importClifford Wolf2013-01-05