path: root/frontends/verilog/parser.y
Commit message (Expand)AuthorAge
* Added defparam support to Verilog/AST frontendClifford Wolf2013-07-04
* More fixes for bugs found using xsthammerClifford Wolf2013-06-13
* Added SAT generator and simple sat_solve commandClifford Wolf2013-06-07
* Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)Clifford Wolf2013-03-31
* Tiny fixes to verilog parserClifford Wolf2013-03-23
* Added support for verilog genblock[index].member syntaxClifford Wolf2013-02-26
* Added support for "always @(*)"Clifford Wolf2013-01-16
* initial importClifford Wolf2013-01-05