index
:
yosys
master
Debian dgit repo for package yosys
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
frontends
/
verilog
/
parser.y
Commit message (
Expand
)
Author
Age
*
Implemented indexed part selects
Clifford Wolf
2013-11-20
*
Implemented part/bit select on memory read
Clifford Wolf
2013-11-20
*
Added init= attribute for fpga-style reset values
Clifford Wolf
2013-11-20
*
Fixed parsing of module arguments when one type is used for many args
Clifford Wolf
2013-11-19
*
Fixed parsing of "parameter integer"
Clifford Wolf
2013-11-13
*
Various fixes for correct parameter support
Clifford Wolf
2013-11-07
*
Fixed handling of boolean attributes (frontends)
Clifford Wolf
2013-10-24
*
Fixed handling of boolean attributes (kernel)
Clifford Wolf
2013-10-24
*
Added defparam support to Verilog/AST frontend
Clifford Wolf
2013-07-04
*
More fixes for bugs found using xsthammer
Clifford Wolf
2013-06-13
*
Added SAT generator and simple sat_solve command
Clifford Wolf
2013-06-07
*
Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)
Clifford Wolf
2013-03-31
*
Tiny fixes to verilog parser
Clifford Wolf
2013-03-23
*
Added support for verilog genblock[index].member syntax
Clifford Wolf
2013-02-26
*
Added support for "always @(*)"
Clifford Wolf
2013-01-16
*
initial import
Clifford Wolf
2013-01-05