path: root/frontends/verilog/parser.y
Commit message (Expand)AuthorAge
* Implemented part/bit select on memory readClifford Wolf2013-11-20
* Added init= attribute for fpga-style reset valuesClifford Wolf2013-11-20
* Fixed parsing of module arguments when one type is used for many argsClifford Wolf2013-11-19
* Fixed parsing of "parameter integer"Clifford Wolf2013-11-13
* Various fixes for correct parameter supportClifford Wolf2013-11-07
* Fixed handling of boolean attributes (frontends)Clifford Wolf2013-10-24
* Fixed handling of boolean attributes (kernel)Clifford Wolf2013-10-24
* Added defparam support to Verilog/AST frontendClifford Wolf2013-07-04
* More fixes for bugs found using xsthammerClifford Wolf2013-06-13
* Added SAT generator and simple sat_solve commandClifford Wolf2013-06-07
* Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)Clifford Wolf2013-03-31
* Tiny fixes to verilog parserClifford Wolf2013-03-23
* Added support for verilog genblock[index].member syntaxClifford Wolf2013-02-26
* Added support for "always @(*)"Clifford Wolf2013-01-16
* initial importClifford Wolf2013-01-05