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verilog
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parser.y
Commit message (
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Author
Age
*
fixed parsing of constant with comment between size and value
Clifford Wolf
2014-07-02
*
Fixed parsing of TOK_INTEGER (implies TOK_SIGNED)
Clifford Wolf
2014-06-16
*
Added handling of real-valued parameters/localparams
Clifford Wolf
2014-06-14
*
Added Verilog lexer and parser support for real values
Clifford Wolf
2014-06-13
*
Added read_verilog -sv options, added support for bit, logic,
Clifford Wolf
2014-06-12
*
Add support for cell arrays
Clifford Wolf
2014-06-07
*
made the generate..endgenrate keywords optional
Clifford Wolf
2014-06-06
*
added while and repeat support to verilog parser
Clifford Wolf
2014-06-06
*
Replaced depricated %name-prefix= bison directive
Clifford Wolf
2014-04-20
*
Added Verilog support for "`default_nettype none"
Clifford Wolf
2014-02-17
*
Added support for functions returning integer
Clifford Wolf
2014-02-12
*
Added constant size expression support of sized constants
Clifford Wolf
2014-02-01
*
Added Verilog parser support for asserts
Clifford Wolf
2014-01-19
*
Added proper === and !== support in constant expressions
Clifford Wolf
2013-12-27
*
Added AstNode::mkconst_str API
Clifford Wolf
2013-12-05
*
Various improvements in support for generate statements
Clifford Wolf
2013-12-04
*
Added support for local regs in named blocks
Clifford Wolf
2013-12-04
*
Improved handling of initialized registers
Clifford Wolf
2013-11-23
*
Implemented indexed part selects
Clifford Wolf
2013-11-20
*
Implemented part/bit select on memory read
Clifford Wolf
2013-11-20
*
Added init= attribute for fpga-style reset values
Clifford Wolf
2013-11-20
*
Fixed parsing of module arguments when one type is used for many args
Clifford Wolf
2013-11-19
*
Fixed parsing of "parameter integer"
Clifford Wolf
2013-11-13
*
Various fixes for correct parameter support
Clifford Wolf
2013-11-07
*
Fixed handling of boolean attributes (frontends)
Clifford Wolf
2013-10-24
*
Fixed handling of boolean attributes (kernel)
Clifford Wolf
2013-10-24
*
Added defparam support to Verilog/AST frontend
Clifford Wolf
2013-07-04
*
More fixes for bugs found using xsthammer
Clifford Wolf
2013-06-13
*
Added SAT generator and simple sat_solve command
Clifford Wolf
2013-06-07
*
Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)
Clifford Wolf
2013-03-31
*
Tiny fixes to verilog parser
Clifford Wolf
2013-03-23
*
Added support for verilog genblock[index].member syntax
Clifford Wolf
2013-02-26
*
Added support for "always @(*)"
Clifford Wolf
2013-01-16
*
initial import
Clifford Wolf
2013-01-05