summaryrefslogtreecommitdiff
path: root/frontends/verilog/preproc.cc
Commit message (Expand)AuthorAge
* New upstream version 0.7+20180830git0b7a184Ruben Undheim2018-08-30
* SystemVerilog also has assume(), added implicit -D FORMALClifford Wolf2015-10-13
* Fixed trailing whitespacesClifford Wolf2015-07-02
* Fixed handling of "//" in filenames in verilog pre-processorClifford Wolf2015-02-14
* Define YOSYS and SYNTHESIS in preprocClifford Wolf2015-01-02
* Re-introduced Yosys::readsome() helper functionClifford Wolf2014-10-23
* Replaced readsome() with read() and gcount()Clifford Wolf2014-10-15
* Fixed win32 troubles with f.readsome()Clifford Wolf2014-10-11
* Added format __attribute__ to stringf()Clifford Wolf2014-10-10
* Changed frontend-api from FILE to std::istreamClifford Wolf2014-08-23
* Fixed line numbers when using here-doc macrosClifford Wolf2014-08-14
* Added support for non-standard """ macro bodiesClifford Wolf2014-08-13
* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-31
* Fixed counting verilog line numbers for "// synopsys translate_off" sectionsClifford Wolf2014-07-30
* Fixed Verilog pre-processor for files with no trailing newlineClifford Wolf2014-07-29
* Using log_assert() instead of assert()Clifford Wolf2014-07-28
* Added Verilog support for "`default_nettype none"Clifford Wolf2014-02-17
* Fixed parsing of verilog macros at end of lineClifford Wolf2014-01-18
* Fixed parsing of non-arg macro calls followed by "("Clifford Wolf2013-12-27
* Fixed parsing of macros with no arguments and expansion text starting with "("Clifford Wolf2013-12-27
* Added elsif preproc supportClifford Wolf2013-12-18
* Added support for macro argumentsClifford Wolf2013-12-18
* Fixed O(n^2) performance bug in verilog preprocessorClifford Wolf2013-11-22
* Enable {* .. *} feature per default (removes dependency to REJECT feature in ...Clifford Wolf2013-11-22
* Added support for include directories with the new '-I' argument of theJohann Glaser2013-08-20
* added option '-Dname[=definition]' to command 'read_verilog'Johann Glaser2013-05-19
* initial importClifford Wolf2013-01-05