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path: root/frontends/verilog/verilog_frontend.cc
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* Added non-std verilog assume() statementClifford Wolf2015-02-26
* Added "read_verilog -nomeminit" and "nomeminit" attributeClifford Wolf2015-02-14
* Print "SystemVerilog" in "read_verilog -sv" log messagesClifford Wolf2014-10-16
* namespace YosysClifford Wolf2014-09-27
* Removed compatbility.{h,cc}: Not using open_memstream/fmemopen anymoreClifford Wolf2014-08-23
* Changed frontend-api from FILE to std::istreamClifford Wolf2014-08-23
* Added support for global tasks and functionsClifford Wolf2014-08-21
* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-31
* Using log_assert() instead of assert()Clifford Wolf2014-07-28
* Added read_verilog -sv options, added support for bit, logic,Clifford Wolf2014-06-12
* Improved error message for options after front-end filename argumentsClifford Wolf2014-06-04
* Merged OSX fixes from Siesh1oo with some modificationsClifford Wolf2014-03-13
* Added Verilog support for "`default_nettype none"Clifford Wolf2014-02-17
* Added a warning note about error reporting to read_verilog help messageClifford Wolf2014-02-16
* Implemented read_verilog -deferClifford Wolf2014-02-13
* Added read_verilog -setattrClifford Wolf2014-02-05
* Added support for blanks after -I and -D in read_verilogClifford Wolf2014-02-02
* Added read_verilog -icells optionClifford Wolf2014-01-29
* Added verilog_defaults commandClifford Wolf2014-01-17
* Added verilog frontend -ignore_redef optionClifford Wolf2013-11-24
* Renamed "placeholder" to "blackbox"Clifford Wolf2013-11-22
* Enable {* .. *} feature per default (removes dependency to REJECT feature in ...Clifford Wolf2013-11-22
* Added support for include directories with the new '-I' argument of theJohann Glaser2013-08-20
* Improved ast dumping (ast/verilog frontend)Clifford Wolf2013-08-19
* Enabled AST/Verilog front-end optimizations per defaultClifford Wolf2013-06-10
* added option '-Dname[=definition]' to command 'read_verilog'Johann Glaser2013-05-19
* Implemented proper handling of stub placeholder modulesClifford Wolf2013-03-28
* Added mem2reg option to verilog frontendClifford Wolf2013-03-24
* Added help messages to ilang and verilog frontendsClifford Wolf2013-03-01
* Moved stand-alone libs to libs/ directory and added libs/subcircuitClifford Wolf2013-02-27
* initial importClifford Wolf2013-01-05