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frontends
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verilog
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verilog_frontend.h
Commit message (
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Author
Age
*
New upstream version 0.9
Ruben Undheim
2019-10-18
*
Imported GIT HEAD: 0.8+20190328git32bd0f2
Ruben Undheim
2019-03-28
*
New upstream version 0.8
Ruben Undheim
2018-10-17
*
New upstream version 0.7+20181007git9850de4
Ruben Undheim
2018-10-15
*
New upstream version 0.7+20180830git0b7a184
Ruben Undheim
2018-08-30
*
Squashed commit of the following:
Ruben Undheim
2016-09-23
*
Fixed trailing whitespaces
Clifford Wolf
2015-07-02
*
Added non-std verilog assume() statement
Clifford Wolf
2015-02-26
*
Added warning for use of 'z' constants in HDL
Clifford Wolf
2014-11-14
*
Changed frontend-api from FILE to std::istream
Clifford Wolf
2014-08-23
*
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
Clifford Wolf
2014-07-31
*
Added read_verilog -sv options, added support for bit, logic,
Clifford Wolf
2014-06-12
*
Added Verilog support for "`default_nettype none"
Clifford Wolf
2014-02-17
*
Enable {* .. *} feature per default (removes dependency to REJECT feature in ...
Clifford Wolf
2013-11-22
*
Added support for include directories with the new '-I' argument of the
Johann Glaser
2013-08-20
*
added option '-Dname[=definition]' to command 'read_verilog'
Johann Glaser
2013-05-19
*
initial import
Clifford Wolf
2013-01-05