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path: root/frontends/verilog/verilog_frontend.h
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* New upstream version 0.9Ruben Undheim2019-10-18
* Imported GIT HEAD: 0.8+20190328git32bd0f2Ruben Undheim2019-03-28
* New upstream version 0.8Ruben Undheim2018-10-17
* New upstream version 0.7+20181007git9850de4Ruben Undheim2018-10-15
* New upstream version 0.7+20180830git0b7a184Ruben Undheim2018-08-30
* Squashed commit of the following:Ruben Undheim2016-09-23
* Fixed trailing whitespacesClifford Wolf2015-07-02
* Added non-std verilog assume() statementClifford Wolf2015-02-26
* Added warning for use of 'z' constants in HDLClifford Wolf2014-11-14
* Changed frontend-api from FILE to std::istreamClifford Wolf2014-08-23
* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-31
* Added read_verilog -sv options, added support for bit, logic,Clifford Wolf2014-06-12
* Added Verilog support for "`default_nettype none"Clifford Wolf2014-02-17
* Enable {* .. *} feature per default (removes dependency to REJECT feature in ...Clifford Wolf2013-11-22
* Added support for include directories with the new '-I' argument of theJohann Glaser2013-08-20
* added option '-Dname[=definition]' to command 'read_verilog'Johann Glaser2013-05-19
* initial importClifford Wolf2013-01-05