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verilog
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verilog_parser.y
Commit message (
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Author
Age
*
New upstream version 0.9
Ruben Undheim
2019-10-18
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Imported GIT HEAD: 0.8+20190328git32bd0f2
Ruben Undheim
2019-03-28
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New upstream version 0.8
Ruben Undheim
2018-10-17
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New upstream version 0.7+20181007git9850de4
Ruben Undheim
2018-10-15
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New upstream version 0.7+20180830git0b7a184
Ruben Undheim
2018-08-30
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Imported yosys 0.7
Ruben Undheim
2016-11-03
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Squashed commit of the following:
Ruben Undheim
2016-09-23
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Fixed handling of parameters and localparams in functions
Clifford Wolf
2015-11-11
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Fixed bug in verilog parser
Clifford Wolf
2015-10-15
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Added support for "parameter" and "localparam" in global context
Clifford Wolf
2015-10-07
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Fixed detection of "task foo(bar);" syntax error
Clifford Wolf
2015-09-22
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Adjust makefiles to work with out-of-tree builds
Clifford Wolf
2015-08-12
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Fixed trailing whitespaces
Clifford Wolf
2015-07-02
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Added non-std verilog assume() statement
Clifford Wolf
2015-02-26
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Parser support for complex delay expressions
Clifford Wolf
2015-02-20
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YosysJS stuff
Clifford Wolf
2015-02-19
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Improved read_verilog support for empty behavioral statements
Clifford Wolf
2015-02-10
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Fixed supply0/supply1 with many wires
Clifford Wolf
2014-12-11
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Added warning for use of 'z' constants in HDL
Clifford Wolf
2014-11-14
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Fixed parsing of nested verilog concatenation and replicate
Clifford Wolf
2014-11-12
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Fixed parsing of "module mymod #( parameter foo = 1, bar = 2 ..."
Clifford Wolf
2014-10-30
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Added support for task and function args in parentheses
Clifford Wolf
2014-10-27
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Updated lexers & parsers to include prefixes
William Speirs
2014-10-15