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path: root/frontends/verilog/verilog_parser.y
Commit message (Collapse)AuthorAge
* Fixed supply0/supply1 with many wiresClifford Wolf2014-12-11
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* Added warning for use of 'z' constants in HDLClifford Wolf2014-11-14
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* Fixed parsing of nested verilog concatenation and replicateClifford Wolf2014-11-12
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* Fixed parsing of "module mymod #( parameter foo = 1, bar = 2 ..."Clifford Wolf2014-10-30
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* Added support for task and function args in parenthesesClifford Wolf2014-10-27
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* Updated lexers & parsers to include prefixesWilliam Speirs2014-10-15