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path: root/frontends/verilog/verilog_parser.y
Commit message (Expand)AuthorAge
* Added non-std verilog assume() statementClifford Wolf2015-02-26
* Parser support for complex delay expressionsClifford Wolf2015-02-20
* YosysJS stuffClifford Wolf2015-02-19
* Improved read_verilog support for empty behavioral statementsClifford Wolf2015-02-10
* Fixed supply0/supply1 with many wiresClifford Wolf2014-12-11
* Added warning for use of 'z' constants in HDLClifford Wolf2014-11-14
* Fixed parsing of nested verilog concatenation and replicateClifford Wolf2014-11-12
* Fixed parsing of "module mymod #( parameter foo = 1, bar = 2 ..."Clifford Wolf2014-10-30
* Added support for task and function args in parenthesesClifford Wolf2014-10-27
* Updated lexers & parsers to include prefixesWilliam Speirs2014-10-15