Commit message (Expand) | Author | Age | |
---|---|---|---|
* | Added non-std verilog assume() statement | Clifford Wolf | 2015-02-26 |
* | Parser support for complex delay expressions | Clifford Wolf | 2015-02-20 |
* | YosysJS stuff | Clifford Wolf | 2015-02-19 |
* | Improved read_verilog support for empty behavioral statements | Clifford Wolf | 2015-02-10 |
* | Fixed supply0/supply1 with many wires | Clifford Wolf | 2014-12-11 |
* | Added warning for use of 'z' constants in HDL | Clifford Wolf | 2014-11-14 |
* | Fixed parsing of nested verilog concatenation and replicate | Clifford Wolf | 2014-11-12 |
* | Fixed parsing of "module mymod #( parameter foo = 1, bar = 2 ..." | Clifford Wolf | 2014-10-30 |
* | Added support for task and function args in parentheses | Clifford Wolf | 2014-10-27 |
* | Updated lexers & parsers to include prefixes | William Speirs | 2014-10-15 |