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* Added support for non-standard "module mod_name(...);" syntaxClifford Wolf2014-08-04
* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-31
* Fixed counting verilog line numbers for "// synopsys translate_off" sectionsClifford Wolf2014-07-30
* Fixed Verilog pre-processor for files with no trailing newlineClifford Wolf2014-07-29
* Using log_assert() instead of assert()Clifford Wolf2014-07-28
* Added "make PRETTY=1"Clifford Wolf2014-07-24
* fixed parsing of constant with comment between size and valueClifford Wolf2014-07-02
* Fixed parsing of TOK_INTEGER (implies TOK_SIGNED)Clifford Wolf2014-06-16
* Improved parsing of large integer constantsClifford Wolf2014-06-15
* Added handling of real-valued parameters/localparamsClifford Wolf2014-06-14
* Added Verilog lexer and parser support for real valuesClifford Wolf2014-06-13
* Added read_verilog -sv options, added support for bit, logic,Clifford Wolf2014-06-12
* Add support for cell arraysClifford Wolf2014-06-07
* made the generate..endgenrate keywords optionalClifford Wolf2014-06-06
* added while and repeat support to verilog parserClifford Wolf2014-06-06
* Improved error message for options after front-end filename argumentsClifford Wolf2014-06-04
* Fixed clang -Wdeprecated-register warningsClifford Wolf2014-04-20
* Replaced depricated %name-prefix= bison directiveClifford Wolf2014-04-20
* Merged OSX fixes from Siesh1oo with some modificationsClifford Wolf2014-03-13
* Added support for `line compiler directiveClifford Wolf2014-03-11
* Added Verilog support for "`default_nettype none"Clifford Wolf2014-02-17
* Added a warning note about error reporting to read_verilog help messageClifford Wolf2014-02-16
* Implemented read_verilog -deferClifford Wolf2014-02-13
* Added support for functions returning integerClifford Wolf2014-02-12
* Added read_verilog -setattrClifford Wolf2014-02-05
* Added support for blanks after -I and -D in read_verilogClifford Wolf2014-02-02
* Added constant size expression support of sized constantsClifford Wolf2014-02-01
* Added read_verilog -icells optionClifford Wolf2014-01-29
* Fixed handling of unsized constants in verilog frontendClifford Wolf2014-01-24
* Added Verilog parser support for assertsClifford Wolf2014-01-19
* Fixed parsing of verilog macros at end of lineClifford Wolf2014-01-18
* Added verilog_defaults commandClifford Wolf2014-01-17
* Fixed parsing of non-arg macro calls followed by "("Clifford Wolf2013-12-27
* Fixed parsing of macros with no arguments and expansion text starting with "("Clifford Wolf2013-12-27
* Added proper === and !== support in constant expressionsClifford Wolf2013-12-27
* Added elsif preproc supportClifford Wolf2013-12-18
* Added support for macro argumentsClifford Wolf2013-12-18
* Added AstNode::mkconst_str APIClifford Wolf2013-12-05
* Various improvements in support for generate statementsClifford Wolf2013-12-04
* Added support for local regs in named blocksClifford Wolf2013-12-04
* Added verilog frontend -ignore_redef optionClifford Wolf2013-11-24
* Improved handling of initialized registersClifford Wolf2013-11-23
* Renamed "placeholder" to "blackbox"Clifford Wolf2013-11-22
* Fixed O(n^2) performance bug in verilog preprocessorClifford Wolf2013-11-22
* Enable {* .. *} feature per default (removes dependency to REJECT feature in ...Clifford Wolf2013-11-22
* Implemented indexed part selectsClifford Wolf2013-11-20
* Added "synthesis" in (synopsys|synthesis) comment supportClifford Wolf2013-11-20
* Implemented part/bit select on memory readClifford Wolf2013-11-20
* Added init= attribute for fpga-style reset valuesClifford Wolf2013-11-20
* Fixed parsing of module arguments when one type is used for many argsClifford Wolf2013-11-19