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* Major redesign of expr width/sign detecion (verilog/ast frontend)Clifford Wolf2013-07-09
* Added defparam support to Verilog/AST frontendClifford Wolf2013-07-04
* More fixes for bugs found using xsthammerClifford Wolf2013-06-13
* Further improved and extended xsthammerClifford Wolf2013-06-11
* Enabled AST/Verilog front-end optimizations per defaultClifford Wolf2013-06-10
* Added SAT generator and simple sat_solve commandClifford Wolf2013-06-07
* added option '-Dname[=definition]' to command 'read_verilog'Johann Glaser2013-05-19
* Added support for verilog === operatorClifford Wolf2013-05-07
* Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)Clifford Wolf2013-03-31
* Implemented proper handling of stub placeholder modulesClifford Wolf2013-03-28
* Improvements and bugfixes for generate blocks with local signalsClifford Wolf2013-03-26
* Added mem2reg option to verilog frontendClifford Wolf2013-03-24
* Tiny fixes to verilog parserClifford Wolf2013-03-23
* Added help messages to ilang and verilog frontendsClifford Wolf2013-03-01
* Moved stand-alone libs to libs/ directory and added libs/subcircuitClifford Wolf2013-02-27
* Added support for verilog genblock[index].member syntaxClifford Wolf2013-02-26
* Added support for "always @(*)"Clifford Wolf2013-01-16
* added .gitignore filesClifford Wolf2013-01-05
* initial importClifford Wolf2013-01-05