yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Added support for non-standard "module mod_name(...);" syntax	Clifford Wolf	2014-08-04
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*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31
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*	Fixed counting verilog line numbers for "// synopsys translate_off" sections	Clifford Wolf	2014-07-30
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*	Fixed Verilog pre-processor for files with no trailing newline	Clifford Wolf	2014-07-29
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*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28
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*	Added "make PRETTY=1"	Clifford Wolf	2014-07-24
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*	fixed parsing of constant with comment between size and value	Clifford Wolf	2014-07-02
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*	Fixed parsing of TOK_INTEGER (implies TOK_SIGNED)	Clifford Wolf	2014-06-16
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*	Improved parsing of large integer constants	Clifford Wolf	2014-06-15
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*	Added handling of real-valued parameters/localparams	Clifford Wolf	2014-06-14
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*	Added Verilog lexer and parser support for real values	Clifford Wolf	2014-06-13
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*	Added read_verilog -sv options, added support for bit, logic,	Clifford Wolf	2014-06-12
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*	Add support for cell arrays	Clifford Wolf	2014-06-07
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*	made the generate..endgenrate keywords optional	Clifford Wolf	2014-06-06
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*	added while and repeat support to verilog parser	Clifford Wolf	2014-06-06
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*	Improved error message for options after front-end filename arguments	Clifford Wolf	2014-06-04
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*	Fixed clang -Wdeprecated-register warnings	Clifford Wolf	2014-04-20
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*	Replaced depricated %name-prefix= bison directive	Clifford Wolf	2014-04-20
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*	Merged OSX fixes from Siesh1oo with some modifications	Clifford Wolf	2014-03-13
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*	Added support for `line compiler directive	Clifford Wolf	2014-03-11
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*	Added Verilog support for "`default_nettype none"	Clifford Wolf	2014-02-17
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*	Added a warning note about error reporting to read_verilog help message	Clifford Wolf	2014-02-16
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*	Implemented read_verilog -defer	Clifford Wolf	2014-02-13
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*	Added support for functions returning integer	Clifford Wolf	2014-02-12
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*	Added read_verilog -setattr	Clifford Wolf	2014-02-05
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*	Added support for blanks after -I and -D in read_verilog	Clifford Wolf	2014-02-02
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*	Added constant size expression support of sized constants	Clifford Wolf	2014-02-01
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*	Added read_verilog -icells option	Clifford Wolf	2014-01-29
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*	Fixed handling of unsized constants in verilog frontend	Clifford Wolf	2014-01-24
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*	Added Verilog parser support for asserts	Clifford Wolf	2014-01-19
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*	Fixed parsing of verilog macros at end of line	Clifford Wolf	2014-01-18
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*	Added verilog_defaults command	Clifford Wolf	2014-01-17
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*	Fixed parsing of non-arg macro calls followed by "("	Clifford Wolf	2013-12-27
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*	Fixed parsing of macros with no arguments and expansion text starting with "("	Clifford Wolf	2013-12-27
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*	Added proper === and !== support in constant expressions	Clifford Wolf	2013-12-27
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*	Added elsif preproc support	Clifford Wolf	2013-12-18
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*	Added support for macro arguments	Clifford Wolf	2013-12-18
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*	Added AstNode::mkconst_str API	Clifford Wolf	2013-12-05
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*	Various improvements in support for generate statements	Clifford Wolf	2013-12-04
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*	Added support for local regs in named blocks	Clifford Wolf	2013-12-04
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*	Added verilog frontend -ignore_redef option	Clifford Wolf	2013-11-24
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*	Improved handling of initialized registers	Clifford Wolf	2013-11-23
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*	Renamed "placeholder" to "blackbox"	Clifford Wolf	2013-11-22
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*	Fixed O(n^2) performance bug in verilog preprocessor	Clifford Wolf	2013-11-22
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*	Enable {* .. *} feature per default (removes dependency to REJECT feature in ↵	Clifford Wolf	2013-11-22
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*	Implemented indexed part selects	Clifford Wolf	2013-11-20
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*	Added "synthesis" in (synopsys\|synthesis) comment support	Clifford Wolf	2013-11-20
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*	Implemented part/bit select on memory read	Clifford Wolf	2013-11-20
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*	Added init= attribute for fpga-style reset values	Clifford Wolf	2013-11-20
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*	Fixed parsing of module arguments when one type is used for many args	Clifford Wolf	2013-11-19
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