yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Define YOSYS and SYNTHESIS in preproc	Clifford Wolf	2015-01-02
*	Improved some warning messages	Clifford Wolf	2014-12-27
*	Fixed supply0/supply1 with many wires	Clifford Wolf	2014-12-11
*	Fixed minor bug in parsing delays	Clifford Wolf	2014-11-24
*	Fixed two minor bugs in constant parsing	Clifford Wolf	2014-11-24
*	Added warning for use of 'z' constants in HDL	Clifford Wolf	2014-11-14
*	Fixed parsing of nested verilog concatenation and replicate	Clifford Wolf	2014-11-12
*	Added log_warning() API	Clifford Wolf	2014-11-09
*	Fixed parsing of "module mymod #( parameter foo = 1, bar = 2 ..."	Clifford Wolf	2014-10-30
*	Added support for task and function args in parentheses	Clifford Wolf	2014-10-27
*	Re-introduced Yosys::readsome() helper function	Clifford Wolf	2014-10-23
*	Print "SystemVerilog" in "read_verilog -sv" log messages	Clifford Wolf	2014-10-16
*	Updated .gitignore file for ilang and verilog frontends	Clifford Wolf	2014-10-15
*	Replaced readsome() with read() and gcount()	Clifford Wolf	2014-10-15
*	Updated lexers & parsers to include prefixes	William Speirs	2014-10-15
*	Fixed win32 troubles with f.readsome()	Clifford Wolf	2014-10-11
*	Added format __attribute__ to stringf()	Clifford Wolf	2014-10-10
*	Renamed SIZE() to GetSize() because of name collision on Win32	Clifford Wolf	2014-10-10
*	namespace Yosys	Clifford Wolf	2014-09-27
*	Removed compatbility.{h,cc}: Not using open_memstream/fmemopen anymore	Clifford Wolf	2014-08-23
*	Changed frontend-api from FILE to std::istream	Clifford Wolf	2014-08-23
*	Added support for non-standard <plugin>:<c_name> DPI syntax	Clifford Wolf	2014-08-22
*	Added support for DPI function with different names in C and Verilog	Clifford Wolf	2014-08-21
*	Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)	Clifford Wolf	2014-08-21
*	Added support for global tasks and functions	Clifford Wolf	2014-08-21
*	Added "via_celltype" attribute on task/func	Clifford Wolf	2014-08-18
*	Fixed line numbers when using here-doc macros	Clifford Wolf	2014-08-14
*	Added support for non-standard """ macro bodies	Clifford Wolf	2014-08-13
*	Also allow "module foobar(input foo, output bar, ...);" syntax	Clifford Wolf	2014-08-07
*	Added AST_MULTIRANGE (arrays with more than 1 dimension)	Clifford Wolf	2014-08-06
*	Improved scope resolution of local regs in Verilog+AST frontend	Clifford Wolf	2014-08-05
*	Added support for non-standard "module mod_name(...);" syntax	Clifford Wolf	2014-08-04
*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31
*	Fixed counting verilog line numbers for "// synopsys translate_off" sections	Clifford Wolf	2014-07-30
*	Fixed Verilog pre-processor for files with no trailing newline	Clifford Wolf	2014-07-29
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28
*	Added "make PRETTY=1"	Clifford Wolf	2014-07-24
*	fixed parsing of constant with comment between size and value	Clifford Wolf	2014-07-02
*	Fixed parsing of TOK_INTEGER (implies TOK_SIGNED)	Clifford Wolf	2014-06-16
*	Improved parsing of large integer constants	Clifford Wolf	2014-06-15
*	Added handling of real-valued parameters/localparams	Clifford Wolf	2014-06-14
*	Added Verilog lexer and parser support for real values	Clifford Wolf	2014-06-13
*	Added read_verilog -sv options, added support for bit, logic,	Clifford Wolf	2014-06-12
*	Add support for cell arrays	Clifford Wolf	2014-06-07
*	made the generate..endgenrate keywords optional	Clifford Wolf	2014-06-06
*	added while and repeat support to verilog parser	Clifford Wolf	2014-06-06
*	Improved error message for options after front-end filename arguments	Clifford Wolf	2014-06-04
*	Fixed clang -Wdeprecated-register warnings	Clifford Wolf	2014-04-20
*	Replaced depricated %name-prefix= bison directive	Clifford Wolf	2014-04-20
*	Merged OSX fixes from Siesh1oo with some modifications	Clifford Wolf	2014-03-13