yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Added Verilog support for "`default_nettype none"	Clifford Wolf	2014-02-17
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*	Added a warning note about error reporting to read_verilog help message	Clifford Wolf	2014-02-16
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*	Implemented read_verilog -defer	Clifford Wolf	2014-02-13
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*	Added support for functions returning integer	Clifford Wolf	2014-02-12
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*	Added read_verilog -setattr	Clifford Wolf	2014-02-05
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*	Added support for blanks after -I and -D in read_verilog	Clifford Wolf	2014-02-02
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*	Added constant size expression support of sized constants	Clifford Wolf	2014-02-01
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*	Added read_verilog -icells option	Clifford Wolf	2014-01-29
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*	Fixed handling of unsized constants in verilog frontend	Clifford Wolf	2014-01-24
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*	Added Verilog parser support for asserts	Clifford Wolf	2014-01-19
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*	Fixed parsing of verilog macros at end of line	Clifford Wolf	2014-01-18
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*	Added verilog_defaults command	Clifford Wolf	2014-01-17
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*	Fixed parsing of non-arg macro calls followed by "("	Clifford Wolf	2013-12-27
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*	Fixed parsing of macros with no arguments and expansion text starting with "("	Clifford Wolf	2013-12-27
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*	Added proper === and !== support in constant expressions	Clifford Wolf	2013-12-27
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*	Added elsif preproc support	Clifford Wolf	2013-12-18
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*	Added support for macro arguments	Clifford Wolf	2013-12-18
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*	Added AstNode::mkconst_str API	Clifford Wolf	2013-12-05
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*	Various improvements in support for generate statements	Clifford Wolf	2013-12-04
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*	Added support for local regs in named blocks	Clifford Wolf	2013-12-04
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*	Added verilog frontend -ignore_redef option	Clifford Wolf	2013-11-24
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*	Improved handling of initialized registers	Clifford Wolf	2013-11-23
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*	Renamed "placeholder" to "blackbox"	Clifford Wolf	2013-11-22
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*	Fixed O(n^2) performance bug in verilog preprocessor	Clifford Wolf	2013-11-22
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*	Enable {* .. *} feature per default (removes dependency to REJECT feature in ↵	Clifford Wolf	2013-11-22
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*	Implemented indexed part selects	Clifford Wolf	2013-11-20
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*	Added "synthesis" in (synopsys\|synthesis) comment support	Clifford Wolf	2013-11-20
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*	Implemented part/bit select on memory read	Clifford Wolf	2013-11-20
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*	Added init= attribute for fpga-style reset values	Clifford Wolf	2013-11-20
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*	Fixed parsing of module arguments when one type is used for many args	Clifford Wolf	2013-11-19
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*	Fixed parsing of "parameter integer"	Clifford Wolf	2013-11-13
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*	Various fixes for correct parameter support	Clifford Wolf	2013-11-07
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*	Fixed handling of boolean attributes (frontends)	Clifford Wolf	2013-10-24
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*	Fixed handling of boolean attributes (kernel)	Clifford Wolf	2013-10-24
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*	fixed Verilog parser filename and line numbering issue with include files	Johann Glaser	2013-08-21
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*	Added support for include directories with the new '-I' argument of the	Johann Glaser	2013-08-20
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*	Added support for notif0/notif1 primitives	Johann Glaser	2013-08-20
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*	Added support for bufif0/bufif1 primitives	Clifford Wolf	2013-08-19
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*	Improved ast dumping (ast/verilog frontend)	Clifford Wolf	2013-08-19
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*	Major redesign of expr width/sign detecion (verilog/ast frontend)	Clifford Wolf	2013-07-09
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*	Added defparam support to Verilog/AST frontend	Clifford Wolf	2013-07-04
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*	More fixes for bugs found using xsthammer	Clifford Wolf	2013-06-13
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*	Further improved and extended xsthammer	Clifford Wolf	2013-06-11
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*	Enabled AST/Verilog front-end optimizations per default	Clifford Wolf	2013-06-10
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*	Added SAT generator and simple sat_solve command	Clifford Wolf	2013-06-07
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*	added option '-Dname[=definition]' to command 'read_verilog'	Johann Glaser	2013-05-19
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*	Added support for verilog === operator	Clifford Wolf	2013-05-07
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*	Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)	Clifford Wolf	2013-03-31
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*	Implemented proper handling of stub placeholder modules	Clifford Wolf	2013-03-28
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*	Improvements and bugfixes for generate blocks with local signals	Clifford Wolf	2013-03-26
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