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* Fixed handling of parameters and localparams in functionsClifford Wolf2015-11-11
* Fixed bug in verilog parserClifford Wolf2015-10-15
* SystemVerilog also has assume(), added implicit -D FORMALClifford Wolf2015-10-13
* Added support for "parameter" and "localparam" in global contextClifford Wolf2015-10-07
* Added read_verilog -nodpiClifford Wolf2015-09-23
* Fixed support for $write system taskClifford Wolf2015-09-23
* Fixed detection of "task foo(bar);" syntax errorClifford Wolf2015-09-22
* Fixed segfault on invalid verilog constant 1'b_Clifford Wolf2015-09-22
* Small corrections to const2ast warning messagesClifford Wolf2015-08-17
* Check base-n literals only contain valid digitsFlorian Zeitz2015-08-17
* Warn on literals exceeding the specified bit widthFlorian Zeitz2015-08-17
* Another block of spelling fixesLarry Doolittle2015-08-14
* Re-created command-reference-manual.tex, copied some doc fixes to online helpClifford Wolf2015-08-14
* Spell check (by Larry Doolittle)Clifford Wolf2015-08-14
* Adjust makefiles to work with out-of-tree buildsClifford Wolf2015-08-12
* Fixed handling of [a-fxz?] in decimal constantsClifford Wolf2015-08-11
* Add -noautowire option to verilog frontendMarcus Comstedt2015-08-01
* Fixed trailing whitespacesClifford Wolf2015-07-02
* Verilog front-end: define `BLACKBOX in -lib modeClifford Wolf2015-04-19
* Ignore celldefine directive in verilog front-endClifford Wolf2015-03-25
* Added non-std verilog assume() statementClifford Wolf2015-02-26
* Parser support for complex delay expressionsClifford Wolf2015-02-20
* YosysJS stuffClifford Wolf2015-02-19
* Added "read_verilog -nomeminit" and "nomeminit" attributeClifford Wolf2015-02-14
* Fixed handling of "//" in filenames in verilog pre-processorClifford Wolf2015-02-14
* Improved read_verilog support for empty behavioral statementsClifford Wolf2015-02-10
* Ignoring more system task and functionsClifford Wolf2015-01-15
* Enable bison to be customizedFabio Utzig2015-01-08
* Define YOSYS and SYNTHESIS in preprocClifford Wolf2015-01-02
* Improved some warning messagesClifford Wolf2014-12-27
* Fixed supply0/supply1 with many wiresClifford Wolf2014-12-11
* Fixed minor bug in parsing delaysClifford Wolf2014-11-24
* Fixed two minor bugs in constant parsingClifford Wolf2014-11-24
* Added warning for use of 'z' constants in HDLClifford Wolf2014-11-14
* Fixed parsing of nested verilog concatenation and replicateClifford Wolf2014-11-12
* Added log_warning() APIClifford Wolf2014-11-09
* Fixed parsing of "module mymod #( parameter foo = 1, bar = 2 ..."Clifford Wolf2014-10-30
* Added support for task and function args in parenthesesClifford Wolf2014-10-27
* Re-introduced Yosys::readsome() helper functionClifford Wolf2014-10-23
* Print "SystemVerilog" in "read_verilog -sv" log messagesClifford Wolf2014-10-16
* Updated .gitignore file for ilang and verilog frontendsClifford Wolf2014-10-15
* Replaced readsome() with read() and gcount()Clifford Wolf2014-10-15
* Updated lexers & parsers to include prefixesWilliam Speirs2014-10-15
* Fixed win32 troubles with f.readsome()Clifford Wolf2014-10-11
* Added format __attribute__ to stringf()Clifford Wolf2014-10-10
* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-10
* namespace YosysClifford Wolf2014-09-27
* Removed compatbility.{h,cc}: Not using open_memstream/fmemopen anymoreClifford Wolf2014-08-23
* Changed frontend-api from FILE to std::istreamClifford Wolf2014-08-23
* Added support for non-standard <plugin>:<c_name> DPI syntaxClifford Wolf2014-08-22