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* Added AstNode::mkconst_str APIClifford Wolf2013-12-05
* Various improvements in support for generate statementsClifford Wolf2013-12-04
* Added support for local regs in named blocksClifford Wolf2013-12-04
* Added verilog frontend -ignore_redef optionClifford Wolf2013-11-24
* Improved handling of initialized registersClifford Wolf2013-11-23
* Renamed "placeholder" to "blackbox"Clifford Wolf2013-11-22
* Fixed O(n^2) performance bug in verilog preprocessorClifford Wolf2013-11-22
* Enable {* .. *} feature per default (removes dependency to REJECT feature in ...Clifford Wolf2013-11-22
* Implemented indexed part selectsClifford Wolf2013-11-20
* Added "synthesis" in (synopsys|synthesis) comment supportClifford Wolf2013-11-20
* Implemented part/bit select on memory readClifford Wolf2013-11-20
* Added init= attribute for fpga-style reset valuesClifford Wolf2013-11-20
* Fixed parsing of module arguments when one type is used for many argsClifford Wolf2013-11-19
* Fixed parsing of "parameter integer"Clifford Wolf2013-11-13
* Various fixes for correct parameter supportClifford Wolf2013-11-07
* Fixed handling of boolean attributes (frontends)Clifford Wolf2013-10-24
* Fixed handling of boolean attributes (kernel)Clifford Wolf2013-10-24
* fixed Verilog parser filename and line numbering issue with include filesJohann Glaser2013-08-21
* Added support for include directories with the new '-I' argument of theJohann Glaser2013-08-20
* Added support for notif0/notif1 primitivesJohann Glaser2013-08-20
* Added support for bufif0/bufif1 primitivesClifford Wolf2013-08-19
* Improved ast dumping (ast/verilog frontend)Clifford Wolf2013-08-19
* Major redesign of expr width/sign detecion (verilog/ast frontend)Clifford Wolf2013-07-09
* Added defparam support to Verilog/AST frontendClifford Wolf2013-07-04
* More fixes for bugs found using xsthammerClifford Wolf2013-06-13
* Further improved and extended xsthammerClifford Wolf2013-06-11
* Enabled AST/Verilog front-end optimizations per defaultClifford Wolf2013-06-10
* Added SAT generator and simple sat_solve commandClifford Wolf2013-06-07
* added option '-Dname[=definition]' to command 'read_verilog'Johann Glaser2013-05-19
* Added support for verilog === operatorClifford Wolf2013-05-07
* Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)Clifford Wolf2013-03-31
* Implemented proper handling of stub placeholder modulesClifford Wolf2013-03-28
* Improvements and bugfixes for generate blocks with local signalsClifford Wolf2013-03-26
* Added mem2reg option to verilog frontendClifford Wolf2013-03-24
* Tiny fixes to verilog parserClifford Wolf2013-03-23
* Added help messages to ilang and verilog frontendsClifford Wolf2013-03-01
* Moved stand-alone libs to libs/ directory and added libs/subcircuitClifford Wolf2013-02-27
* Added support for verilog genblock[index].member syntaxClifford Wolf2013-02-26
* Added support for "always @(*)"Clifford Wolf2013-01-16
* added .gitignore filesClifford Wolf2013-01-05
* initial importClifford Wolf2013-01-05