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verilog
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Author
Age
*
Major redesign of expr width/sign detecion (verilog/ast frontend)
Clifford Wolf
2013-07-09
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Added defparam support to Verilog/AST frontend
Clifford Wolf
2013-07-04
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More fixes for bugs found using xsthammer
Clifford Wolf
2013-06-13
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Further improved and extended xsthammer
Clifford Wolf
2013-06-11
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Enabled AST/Verilog front-end optimizations per default
Clifford Wolf
2013-06-10
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Added SAT generator and simple sat_solve command
Clifford Wolf
2013-06-07
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added option '-Dname[=definition]' to command 'read_verilog'
Johann Glaser
2013-05-19
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Added support for verilog === operator
Clifford Wolf
2013-05-07
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Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)
Clifford Wolf
2013-03-31
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Implemented proper handling of stub placeholder modules
Clifford Wolf
2013-03-28
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Improvements and bugfixes for generate blocks with local signals
Clifford Wolf
2013-03-26
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Added mem2reg option to verilog frontend
Clifford Wolf
2013-03-24
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Tiny fixes to verilog parser
Clifford Wolf
2013-03-23
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Added help messages to ilang and verilog frontends
Clifford Wolf
2013-03-01
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Moved stand-alone libs to libs/ directory and added libs/subcircuit
Clifford Wolf
2013-02-27
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Added support for verilog genblock[index].member syntax
Clifford Wolf
2013-02-26
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Added support for "always @(*)"
Clifford Wolf
2013-01-16
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added .gitignore files
Clifford Wolf
2013-01-05
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initial import
Clifford Wolf
2013-01-05