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* Fixed O(n^2) performance bug in verilog preprocessorClifford Wolf2013-11-22
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* Enable {* .. *} feature per default (removes dependency to REJECT feature in ↵Clifford Wolf2013-11-22
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* Implemented indexed part selectsClifford Wolf2013-11-20
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* Added "synthesis" in (synopsys|synthesis) comment supportClifford Wolf2013-11-20
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* Implemented part/bit select on memory readClifford Wolf2013-11-20
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* Added init= attribute for fpga-style reset valuesClifford Wolf2013-11-20
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* Fixed parsing of module arguments when one type is used for many argsClifford Wolf2013-11-19
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* Fixed parsing of "parameter integer"Clifford Wolf2013-11-13
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* Various fixes for correct parameter supportClifford Wolf2013-11-07
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* Fixed handling of boolean attributes (frontends)Clifford Wolf2013-10-24
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* Fixed handling of boolean attributes (kernel)Clifford Wolf2013-10-24
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* fixed Verilog parser filename and line numbering issue with include filesJohann Glaser2013-08-21
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* Added support for include directories with the new '-I' argument of theJohann Glaser2013-08-20
| | | | 'read_verilog' command
* Added support for notif0/notif1 primitivesJohann Glaser2013-08-20
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* Added support for bufif0/bufif1 primitivesClifford Wolf2013-08-19
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* Improved ast dumping (ast/verilog frontend)Clifford Wolf2013-08-19
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* Major redesign of expr width/sign detecion (verilog/ast frontend)Clifford Wolf2013-07-09
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* Added defparam support to Verilog/AST frontendClifford Wolf2013-07-04
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* More fixes for bugs found using xsthammerClifford Wolf2013-06-13
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* Further improved and extended xsthammerClifford Wolf2013-06-11
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* Enabled AST/Verilog front-end optimizations per defaultClifford Wolf2013-06-10
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* Added SAT generator and simple sat_solve commandClifford Wolf2013-06-07
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* added option '-Dname[=definition]' to command 'read_verilog'Johann Glaser2013-05-19
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* Added support for verilog === operatorClifford Wolf2013-05-07
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* Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)Clifford Wolf2013-03-31
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* Implemented proper handling of stub placeholder modulesClifford Wolf2013-03-28
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* Improvements and bugfixes for generate blocks with local signalsClifford Wolf2013-03-26
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* Added mem2reg option to verilog frontendClifford Wolf2013-03-24
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* Tiny fixes to verilog parserClifford Wolf2013-03-23
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* Added help messages to ilang and verilog frontendsClifford Wolf2013-03-01
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* Moved stand-alone libs to libs/ directory and added libs/subcircuitClifford Wolf2013-02-27
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* Added support for verilog genblock[index].member syntaxClifford Wolf2013-02-26
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* Added support for "always @(*)"Clifford Wolf2013-01-16
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* added .gitignore filesClifford Wolf2013-01-05
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* initial importClifford Wolf2013-01-05