yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Fixed parsing of non-arg macro calls followed by "("	Clifford Wolf	2013-12-27
*	Fixed parsing of macros with no arguments and expansion text starting with "("	Clifford Wolf	2013-12-27
*	Added proper === and !== support in constant expressions	Clifford Wolf	2013-12-27
*	Added elsif preproc support	Clifford Wolf	2013-12-18
*	Added support for macro arguments	Clifford Wolf	2013-12-18
*	Added AstNode::mkconst_str API	Clifford Wolf	2013-12-05
*	Various improvements in support for generate statements	Clifford Wolf	2013-12-04
*	Added support for local regs in named blocks	Clifford Wolf	2013-12-04
*	Added verilog frontend -ignore_redef option	Clifford Wolf	2013-11-24
*	Improved handling of initialized registers	Clifford Wolf	2013-11-23
*	Renamed "placeholder" to "blackbox"	Clifford Wolf	2013-11-22
*	Fixed O(n^2) performance bug in verilog preprocessor	Clifford Wolf	2013-11-22
*	Enable {* .. *} feature per default (removes dependency to REJECT feature in ...	Clifford Wolf	2013-11-22
*	Implemented indexed part selects	Clifford Wolf	2013-11-20
*	Added "synthesis" in (synopsys\|synthesis) comment support	Clifford Wolf	2013-11-20
*	Implemented part/bit select on memory read	Clifford Wolf	2013-11-20
*	Added init= attribute for fpga-style reset values	Clifford Wolf	2013-11-20
*	Fixed parsing of module arguments when one type is used for many args	Clifford Wolf	2013-11-19
*	Fixed parsing of "parameter integer"	Clifford Wolf	2013-11-13
*	Various fixes for correct parameter support	Clifford Wolf	2013-11-07
*	Fixed handling of boolean attributes (frontends)	Clifford Wolf	2013-10-24
*	Fixed handling of boolean attributes (kernel)	Clifford Wolf	2013-10-24
*	fixed Verilog parser filename and line numbering issue with include files	Johann Glaser	2013-08-21
*	Added support for include directories with the new '-I' argument of the	Johann Glaser	2013-08-20
*	Added support for notif0/notif1 primitives	Johann Glaser	2013-08-20
*	Added support for bufif0/bufif1 primitives	Clifford Wolf	2013-08-19
*	Improved ast dumping (ast/verilog frontend)	Clifford Wolf	2013-08-19
*	Major redesign of expr width/sign detecion (verilog/ast frontend)	Clifford Wolf	2013-07-09
*	Added defparam support to Verilog/AST frontend	Clifford Wolf	2013-07-04
*	More fixes for bugs found using xsthammer	Clifford Wolf	2013-06-13
*	Further improved and extended xsthammer	Clifford Wolf	2013-06-11
*	Enabled AST/Verilog front-end optimizations per default	Clifford Wolf	2013-06-10
*	Added SAT generator and simple sat_solve command	Clifford Wolf	2013-06-07
*	added option '-Dname[=definition]' to command 'read_verilog'	Johann Glaser	2013-05-19
*	Added support for verilog === operator	Clifford Wolf	2013-05-07
*	Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)	Clifford Wolf	2013-03-31
*	Implemented proper handling of stub placeholder modules	Clifford Wolf	2013-03-28
*	Improvements and bugfixes for generate blocks with local signals	Clifford Wolf	2013-03-26
*	Added mem2reg option to verilog frontend	Clifford Wolf	2013-03-24
*	Tiny fixes to verilog parser	Clifford Wolf	2013-03-23
*	Added help messages to ilang and verilog frontends	Clifford Wolf	2013-03-01
*	Moved stand-alone libs to libs/ directory and added libs/subcircuit	Clifford Wolf	2013-02-27
*	Added support for verilog genblock[index].member syntax	Clifford Wolf	2013-02-26
*	Added support for "always @(*)"	Clifford Wolf	2013-01-16
*	added .gitignore files	Clifford Wolf	2013-01-05
*	initial import	Clifford Wolf	2013-01-05