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* Define YOSYS and SYNTHESIS in preprocClifford Wolf2015-01-02
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* Improved some warning messagesClifford Wolf2014-12-27
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* Fixed supply0/supply1 with many wiresClifford Wolf2014-12-11
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* Fixed minor bug in parsing delaysClifford Wolf2014-11-24
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* Fixed two minor bugs in constant parsingClifford Wolf2014-11-24
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* Added warning for use of 'z' constants in HDLClifford Wolf2014-11-14
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* Fixed parsing of nested verilog concatenation and replicateClifford Wolf2014-11-12
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* Added log_warning() APIClifford Wolf2014-11-09
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* Fixed parsing of "module mymod #( parameter foo = 1, bar = 2 ..."Clifford Wolf2014-10-30
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* Added support for task and function args in parenthesesClifford Wolf2014-10-27
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* Re-introduced Yosys::readsome() helper functionClifford Wolf2014-10-23
| | | | (f.read() + f.gcount() made problems with lines > 16kB)
* Print "SystemVerilog" in "read_verilog -sv" log messagesClifford Wolf2014-10-16
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* Updated .gitignore file for ilang and verilog frontendsClifford Wolf2014-10-15
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* Replaced readsome() with read() and gcount()Clifford Wolf2014-10-15
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* Updated lexers & parsers to include prefixesWilliam Speirs2014-10-15
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* Fixed win32 troubles with f.readsome()Clifford Wolf2014-10-11
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* Added format __attribute__ to stringf()Clifford Wolf2014-10-10
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* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-10
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* namespace YosysClifford Wolf2014-09-27
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* Removed compatbility.{h,cc}: Not using open_memstream/fmemopen anymoreClifford Wolf2014-08-23
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* Changed frontend-api from FILE to std::istreamClifford Wolf2014-08-23
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* Added support for non-standard <plugin>:<c_name> DPI syntaxClifford Wolf2014-08-22
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* Added support for DPI function with different names in C and VerilogClifford Wolf2014-08-21
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* Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)Clifford Wolf2014-08-21
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* Added support for global tasks and functionsClifford Wolf2014-08-21
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* Added "via_celltype" attribute on task/funcClifford Wolf2014-08-18
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* Fixed line numbers when using here-doc macrosClifford Wolf2014-08-14
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* Added support for non-standard """ macro bodiesClifford Wolf2014-08-13
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* Also allow "module foobar(input foo, output bar, ...);" syntaxClifford Wolf2014-08-07
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* Added AST_MULTIRANGE (arrays with more than 1 dimension)Clifford Wolf2014-08-06
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* Improved scope resolution of local regs in Verilog+AST frontendClifford Wolf2014-08-05
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* Added support for non-standard "module mod_name(...);" syntaxClifford Wolf2014-08-04
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* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-31
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* Fixed counting verilog line numbers for "// synopsys translate_off" sectionsClifford Wolf2014-07-30
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* Fixed Verilog pre-processor for files with no trailing newlineClifford Wolf2014-07-29
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* Using log_assert() instead of assert()Clifford Wolf2014-07-28
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* Added "make PRETTY=1"Clifford Wolf2014-07-24
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* fixed parsing of constant with comment between size and valueClifford Wolf2014-07-02
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* Fixed parsing of TOK_INTEGER (implies TOK_SIGNED)Clifford Wolf2014-06-16
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* Improved parsing of large integer constantsClifford Wolf2014-06-15
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* Added handling of real-valued parameters/localparamsClifford Wolf2014-06-14
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* Added Verilog lexer and parser support for real valuesClifford Wolf2014-06-13
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* Added read_verilog -sv options, added support for bit, logic,Clifford Wolf2014-06-12
| | | | allways_ff, always_comb, and always_latch
* Add support for cell arraysClifford Wolf2014-06-07
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* made the generate..endgenrate keywords optionalClifford Wolf2014-06-06
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* added while and repeat support to verilog parserClifford Wolf2014-06-06
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* Improved error message for options after front-end filename argumentsClifford Wolf2014-06-04
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* Fixed clang -Wdeprecated-register warningsClifford Wolf2014-04-20
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* Replaced depricated %name-prefix= bison directiveClifford Wolf2014-04-20
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* Merged OSX fixes from Siesh1oo with some modificationsClifford Wolf2014-03-13
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