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* Fixed AST handling of variables declared inside a functions main blockClifford Wolf2014-08-05
* Added support for non-standard "module mod_name(...);" syntaxClifford Wolf2014-08-04
* More bugfixes related to new RTLIL::IdStringClifford Wolf2014-08-02
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-02
* Preparations for RTLIL::IdString redesign: cleanup of existing codeClifford Wolf2014-08-02
* Replaced sha1 implementationClifford Wolf2014-08-01
* Fixed build of verific bindingsClifford Wolf2014-07-31
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-31
* Added module->design and cell->module, wire->module pointersClifford Wolf2014-07-31
* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-31
* Fixed counting verilog line numbers for "// synopsys translate_off" sectionsClifford Wolf2014-07-30
* Fixed Verilog pre-processor for files with no trailing newlineClifford Wolf2014-07-29
* Added $shift and $shiftx cell types (needed for correct part select behavior)Clifford Wolf2014-07-29
* Removed left over debug codeClifford Wolf2014-07-28
* Fixed part selects of parametersClifford Wolf2014-07-28
* Set results of out-of-bounds static bit/part select to undefClifford Wolf2014-07-28
* Fixed RTLIL code generator for part select of parameterClifford Wolf2014-07-28
* Fixed width detection for part selectsClifford Wolf2014-07-28
* Added support for "upto" wires to Verilog front- and back-endClifford Wolf2014-07-28
* Added wire->upto flag for signals such as "wire [0:7] x;"Clifford Wolf2014-07-28
* Using log_assert() instead of assert()Clifford Wolf2014-07-28
* Fixed signdness detection of expressions with bit- and part-selectsClifford Wolf2014-07-28
* Added proper Design->addModule interfaceClifford Wolf2014-07-27
* Fixed verific bindings for new RTLIL apiClifford Wolf2014-07-27
* Fixed ilang parser for new RTLIL APIClifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-26
* Added RTLIL::Cell::has(portname)Clifford Wolf2014-07-26
* Manual fixes for new cell connections APIClifford Wolf2014-07-26
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-25
* Fixed two memory leaks in ast simplifyClifford Wolf2014-07-25
* Updated verific build/test instructionsClifford Wolf2014-07-25
* Replaced more old SigChunk programming patternsClifford Wolf2014-07-24
* Added "make PRETTY=1"Clifford Wolf2014-07-24
* Various fixes in Verific frontend for new RTLIL APIClifford Wolf2014-07-23
* Various small fixes (from gcc compiler warnings)Clifford Wolf2014-07-23
* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-23
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3Clifford Wolf2014-07-23
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3Clifford Wolf2014-07-23
* SigSpec refactoring: More cleanups of old SigSpec use patternClifford Wolf2014-07-22
* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...Clifford Wolf2014-07-22
* SigSpec refactoring: change RTLIL::SigSpec::size() to be read-onlyClifford Wolf2014-07-22
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
* Fixed ilang parsing of process attributesClifford Wolf2014-07-22
* Fixed make rules for ilang parserClifford Wolf2014-07-22