yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Added correct handling of $memwr priority	Clifford Wolf	2014-01-03
*	Fixed a stupid access after delete bug	Clifford Wolf	2013-12-29
*	Fixed parsing of non-arg macro calls followed by "("	Clifford Wolf	2013-12-27
*	Fixed parsing of macros with no arguments and expansion text starting with "("	Clifford Wolf	2013-12-27
*	Added support for non-const === and !== (for miter circuits)	Clifford Wolf	2013-12-27
*	Added proper === and !== support in constant expressions	Clifford Wolf	2013-12-27
*	Added elsif preproc support	Clifford Wolf	2013-12-18
*	Added support for macro arguments	Clifford Wolf	2013-12-18
*	Keep strings as strings in const ternary and concat	Clifford Wolf	2013-12-05
*	Added const folding support for $signed and $unsigned	Clifford Wolf	2013-12-05
*	Added AstNode::mkconst_str API	Clifford Wolf	2013-12-05
*	Fixed generate-for (and disabled double warning for auto-wire)	Clifford Wolf	2013-12-04
*	Added support for $clog2 system function	Clifford Wolf	2013-12-04
*	Various improvements in support for generate statements	Clifford Wolf	2013-12-04
*	Replaced signed_parameters API with CONST_FLAG_SIGNED	Clifford Wolf	2013-12-04
*	Replaced RTLIL::Const::str with generic decoder method	Clifford Wolf	2013-12-04
*	Added support for local regs in named blocks	Clifford Wolf	2013-12-04
*	Fixed temp net name generation in rtlil process generator for abbreviated nam...	Clifford Wolf	2013-11-28
*	Added "src" attribute to processes	Clifford Wolf	2013-11-28
*	Added module->avail_parameters (for advanced techmap features)	Clifford Wolf	2013-11-24
*	Added verilog frontend -ignore_redef option	Clifford Wolf	2013-11-24
*	Early wire/reg/parameter width calculation in ast/simplify	Clifford Wolf	2013-11-24
*	Added support for signed parameters in ilang	Clifford Wolf	2013-11-24
*	Remove auto_wire framework (smarter than the verilog standard)	Clifford Wolf	2013-11-24
*	Implemented correct handling of signed module parameters	Clifford Wolf	2013-11-24
*	Improved handling of initialized registers	Clifford Wolf	2013-11-23
*	Renamed "placeholder" to "blackbox"	Clifford Wolf	2013-11-22
*	Fixed O(n^2) performance bug in verilog preprocessor	Clifford Wolf	2013-11-22
*	Enable {* .. *} feature per default (removes dependency to REJECT feature in ...	Clifford Wolf	2013-11-22
*	Fixed async proc detection in mem2reg	Clifford Wolf	2013-11-21
*	Major improvements in mem2reg and added "init" sync rules	Clifford Wolf	2013-11-21
*	Fixed ilang parser: memory width	Clifford Wolf	2013-11-20
*	Another name resolution bugfix for generate blocks	Clifford Wolf	2013-11-20
*	Implemented indexed part selects	Clifford Wolf	2013-11-20
*	Do not allow memory bit select on the left side of an assignment	Clifford Wolf	2013-11-20
*	Added "synthesis" in (synopsys\|synthesis) comment support	Clifford Wolf	2013-11-20
*	Fixed name resolution of local tasks and functions in generate block	Clifford Wolf	2013-11-20
*	Implemented part/bit select on memory read	Clifford Wolf	2013-11-20
*	Added init= attribute for fpga-style reset values	Clifford Wolf	2013-11-20
*	Fixed parsing of module arguments when one type is used for many args	Clifford Wolf	2013-11-19
*	Fixed two bugs in mem2reg functionality in AST frontend	Clifford Wolf	2013-11-18
*	Added dumping of attributes in AST frontend	Clifford Wolf	2013-11-18
*	Fixed parsing of default cases when not last case	Clifford Wolf	2013-11-18
*	Fixed mem2reg for reg usage outside always block	Clifford Wolf	2013-11-18
*	Fixed parsing of "parameter integer"	Clifford Wolf	2013-11-13
*	Cleanups and bugfixes in response to new internal cell checker	Clifford Wolf	2013-11-11
*	Call internal checker more often	Clifford Wolf	2013-11-10
*	More undef-propagation related fixes	Clifford Wolf	2013-11-08
*	Fixed handling of different signedness in power operands	Clifford Wolf	2013-11-08
*	Implemented const folding of ternary op with undef select	Clifford Wolf	2013-11-08