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* Added correct handling of $memwr priorityClifford Wolf2014-01-03
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* Fixed a stupid access after delete bugClifford Wolf2013-12-29
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* Fixed parsing of non-arg macro calls followed by "("Clifford Wolf2013-12-27
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* Fixed parsing of macros with no arguments and expansion text starting with "("Clifford Wolf2013-12-27
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* Added support for non-const === and !== (for miter circuits)Clifford Wolf2013-12-27
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* Added proper === and !== support in constant expressionsClifford Wolf2013-12-27
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* Added elsif preproc supportClifford Wolf2013-12-18
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* Added support for macro argumentsClifford Wolf2013-12-18
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* Keep strings as strings in const ternary and concatClifford Wolf2013-12-05
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* Added const folding support for $signed and $unsignedClifford Wolf2013-12-05
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* Added AstNode::mkconst_str APIClifford Wolf2013-12-05
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* Fixed generate-for (and disabled double warning for auto-wire)Clifford Wolf2013-12-04
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* Added support for $clog2 system functionClifford Wolf2013-12-04
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* Various improvements in support for generate statementsClifford Wolf2013-12-04
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* Replaced signed_parameters API with CONST_FLAG_SIGNEDClifford Wolf2013-12-04
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* Replaced RTLIL::Const::str with generic decoder methodClifford Wolf2013-12-04
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* Added support for local regs in named blocksClifford Wolf2013-12-04
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* Fixed temp net name generation in rtlil process generator for abbreviated ↵Clifford Wolf2013-11-28
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* Added "src" attribute to processesClifford Wolf2013-11-28
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* Added module->avail_parameters (for advanced techmap features)Clifford Wolf2013-11-24
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* Added verilog frontend -ignore_redef optionClifford Wolf2013-11-24
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* Early wire/reg/parameter width calculation in ast/simplifyClifford Wolf2013-11-24
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* Added support for signed parameters in ilangClifford Wolf2013-11-24
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* Remove auto_wire framework (smarter than the verilog standard)Clifford Wolf2013-11-24
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* Implemented correct handling of signed module parametersClifford Wolf2013-11-24
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* Improved handling of initialized registersClifford Wolf2013-11-23
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* Renamed "placeholder" to "blackbox"Clifford Wolf2013-11-22
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* Fixed O(n^2) performance bug in verilog preprocessorClifford Wolf2013-11-22
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* Enable {* .. *} feature per default (removes dependency to REJECT feature in ↵Clifford Wolf2013-11-22
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* Fixed async proc detection in mem2regClifford Wolf2013-11-21
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* Major improvements in mem2reg and added "init" sync rulesClifford Wolf2013-11-21
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* Fixed ilang parser: memory widthClifford Wolf2013-11-20
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* Another name resolution bugfix for generate blocksClifford Wolf2013-11-20
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* Implemented indexed part selectsClifford Wolf2013-11-20
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* Do not allow memory bit select on the left side of an assignmentClifford Wolf2013-11-20
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* Added "synthesis" in (synopsys|synthesis) comment supportClifford Wolf2013-11-20
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* Fixed name resolution of local tasks and functions in generate blockClifford Wolf2013-11-20
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* Implemented part/bit select on memory readClifford Wolf2013-11-20
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* Added init= attribute for fpga-style reset valuesClifford Wolf2013-11-20
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* Fixed parsing of module arguments when one type is used for many argsClifford Wolf2013-11-19
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* Fixed two bugs in mem2reg functionality in AST frontendClifford Wolf2013-11-18
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* Added dumping of attributes in AST frontendClifford Wolf2013-11-18
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* Fixed parsing of default cases when not last caseClifford Wolf2013-11-18
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* Fixed mem2reg for reg usage outside always blockClifford Wolf2013-11-18
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* Fixed parsing of "parameter integer"Clifford Wolf2013-11-13
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* Cleanups and bugfixes in response to new internal cell checkerClifford Wolf2013-11-11
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* Call internal checker more oftenClifford Wolf2013-11-10
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* More undef-propagation related fixesClifford Wolf2013-11-08
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* Fixed handling of different signedness in power operandsClifford Wolf2013-11-08
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* Implemented const folding of ternary op with undef selectClifford Wolf2013-11-08
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