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* added option '-Dname[=definition]' to command 'read_verilog'Johann Glaser2013-05-19
* Merge branch 'bugfix'Clifford Wolf2013-05-16
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| * Fixed synthesis of functions in latched blocksClifford Wolf2013-05-16
* | Added support for verilog === operatorClifford Wolf2013-05-07
* | Fixed handling of positional module parametersClifford Wolf2013-04-26
* | Only use sha1 checksums for names of parametric modules when the verbose form...Clifford Wolf2013-04-26
* | Fixed a bug in AST frontend for cases with non-blocking assigned variables as...Clifford Wolf2013-04-13
* | Now only use value from "initial" when no matching "always" block is foundClifford Wolf2013-03-31
* | Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)Clifford Wolf2013-03-31
* | Implemented proper handling of stub placeholder modulesClifford Wolf2013-03-28
* | Improvements and bugfixes for generate blocks with local signalsClifford Wolf2013-03-26
* | Fixed handling of unconditional generate blocksClifford Wolf2013-03-26
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* Added nosync attribute and some async reset related fixesClifford Wolf2013-03-25
* Added mem2reg option to verilog frontendClifford Wolf2013-03-24
* Another fix in mem2reg ast simplify logicClifford Wolf2013-03-24
* Improved mem2reg handling in ast simplifierClifford Wolf2013-03-24
* Tiny fixes to verilog parserClifford Wolf2013-03-23
* Added help messages to ilang and verilog frontendsClifford Wolf2013-03-01
* Moved stand-alone libs to libs/ directory and added libs/subcircuitClifford Wolf2013-02-27
* Added support for verilog genblock[index].member syntaxClifford Wolf2013-02-26
* Added support for "always @(*)"Clifford Wolf2013-01-16
* added .gitignore filesClifford Wolf2013-01-05
* initial importClifford Wolf2013-01-05