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* Added "autoidx" statement to ilang file formatClifford Wolf2014-07-21
* Replaced depricated NEW_WIRE macro with module->addWire() callsClifford Wolf2014-07-21
* Removed deprecated module->new_wire()Clifford Wolf2014-07-21
* Implemented dynamic bit-/part-select for memory writesClifford Wolf2014-07-17
* Added support for bit/part select to mem2reg rewriterClifford Wolf2014-07-17
* Added support for constant bit- or part-select for memory writesClifford Wolf2014-07-17
* Added "inout" ports support to read_libertyClifford Wolf2014-07-16
* Set blackbox attribute in "read_liberty -lib"Clifford Wolf2014-07-16
* Fixed spelling of "direction" in read_liberty messagesClifford Wolf2014-07-16
* changes in verilog frontend for new $mem/$memwr WR_EN interfaceClifford Wolf2014-07-16
* Added passing of various options to vhdl2verilogClifford Wolf2014-07-12
* Fixed processing of initial values for block-local variablesClifford Wolf2014-07-11
* fixed parsing of constant with comment between size and valueClifford Wolf2014-07-02
* Fixed handling of mixed real/int ternary expressionsClifford Wolf2014-06-25
* More found_real-related fixes to AstNode::detectSignWidthWorkerClifford Wolf2014-06-24
* fixed signdness detection for expressions with realsClifford Wolf2014-06-21
* Added AstNode::MEM2REG_FL_CMPLX_LHSClifford Wolf2014-06-17
* Improved handling of relational op of real valuesClifford Wolf2014-06-17
* Improved ternary support for real valuesClifford Wolf2014-06-16
* Use undef (x/z vs. NaN) rules for real values from IEEE Std 1800-2012Clifford Wolf2014-06-16
* Fixed parsing of TOK_INTEGER (implies TOK_SIGNED)Clifford Wolf2014-06-16
* Added found_real feature to AstNode::detectSignWidthClifford Wolf2014-06-16
* Improved AstNode::realAsConst for large numbersClifford Wolf2014-06-15
* Improved parsing of large integer constantsClifford Wolf2014-06-15
* Improved AstNode::asReal for large integersClifford Wolf2014-06-15
* improved (fixed) conversion of real values to bit vectorsClifford Wolf2014-06-14
* Fixed relational operators for const real expressionsClifford Wolf2014-06-14
* Added support for math functionsClifford Wolf2014-06-14
* Added handling of real-valued parameters/localparamsClifford Wolf2014-06-14
* Implemented more real arithmeticClifford Wolf2014-06-14
* Implemented basic real arithmeticClifford Wolf2014-06-14
* Added real->int convertion in ast genrtlilClifford Wolf2014-06-14
* Added Verilog lexer and parser support for real valuesClifford Wolf2014-06-13
* Added read_verilog -sv options, added support for bit, logic,Clifford Wolf2014-06-12
* Add support for cell arraysClifford Wolf2014-06-07
* Added support for repeat stmt in const functionsClifford Wolf2014-06-07
* further improved const function supportClifford Wolf2014-06-07
* made the generate..endgenrate keywords optionalClifford Wolf2014-06-06
* improved const function supportClifford Wolf2014-06-06
* fix functions with no block (but single statement, loop, etc.)Clifford Wolf2014-06-06
* improved ast simplify of const functionsClifford Wolf2014-06-06
* added while and repeat support to verilog parserClifford Wolf2014-06-06
* Improved error message for options after front-end filename argumentsClifford Wolf2014-06-04
* new flags -ignore_miss_func and -ignore_miss_dir for read_libertyJohann Glaser2014-05-28
* Fixed clang -Wdeprecated-register warningsClifford Wolf2014-04-20
* Replaced depricated %name-prefix= bison directiveClifford Wolf2014-04-20
* Fixed mapping of Verific WIDE_DFFRS operatorClifford Wolf2014-03-20
* Fixed mapping of Verific FADD primitive with unconnected outputsClifford Wolf2014-03-20
* Progress in Verific bindingsClifford Wolf2014-03-17
* Progress in Verific bindingsClifford Wolf2014-03-17