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Author
Age
*
Define YOSYS and SYNTHESIS in preproc
Clifford Wolf
2015-01-02
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Fixed memory->start_offset handling
Clifford Wolf
2015-01-01
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Added global yosys_celltypes
Clifford Wolf
2014-12-29
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dict/pool changes in ast
Clifford Wolf
2014-12-29
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Changed more code to dict<> and pool<>
Clifford Wolf
2014-12-28
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Improved some warning messages
Clifford Wolf
2014-12-27
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Fixed mem2reg warning message
Clifford Wolf
2014-12-27
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Added Yosys::{dict,nodict,vector} container types
Clifford Wolf
2014-12-26
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Renamed extend() to extend_xx(), changed most users to extend_u0()
Clifford Wolf
2014-12-24
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Fixed supply0/supply1 with many wires
Clifford Wolf
2014-12-11
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Fixed minor bug in parsing delays
Clifford Wolf
2014-11-24
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Fixed two minor bugs in constant parsing
Clifford Wolf
2014-11-24
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Added warning for use of 'z' constants in HDL
Clifford Wolf
2014-11-14
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Fixed parsing of nested verilog concatenation and replicate
Clifford Wolf
2014-11-12
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Added log_warning() API
Clifford Wolf
2014-11-09
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Added "ENABLE_PLUGINS := 0" to verific amd64 build instructions
Clifford Wolf
2014-11-08
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Fixed parsing of "module mymod #( parameter foo = 1, bar = 2 ..."
Clifford Wolf
2014-10-30
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AST simplifier: optimize constant AST_CASE nodes before recursively descending
Clifford Wolf
2014-10-29
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Added support for task and function args in parentheses
Clifford Wolf
2014-10-27
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Improvements in $readmem[bh] implementation
Clifford Wolf
2014-10-26
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Added support for $readmemh/$readmemb
Clifford Wolf
2014-10-26
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Fixed constant "cond ? string1 : string2" with strings of different size
Clifford Wolf
2014-10-25
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Re-introduced Yosys::readsome() helper function
Clifford Wolf
2014-10-23
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(f.read() + f.gcount() made problems with lines > 16kB)
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minor indenting corrections
Clifford Wolf
2014-10-19
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Builds on Mac 10.9.2 with LLVM 3.5.
Parviz Palangpour
2014-10-19
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Fixed various VS warnings
Clifford Wolf
2014-10-18
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Header changes so it will compile on VS
William Speirs
2014-10-17
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Wrapped math in int constructor
William Speirs
2014-10-17
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Print "SystemVerilog" in "read_verilog -sv" log messages
Clifford Wolf
2014-10-16
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Fixed handling of invalid array access in mem2reg code
Clifford Wolf
2014-10-16
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Updated .gitignore file for ilang and verilog frontends
Clifford Wolf
2014-10-15
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Replaced readsome() with read() and gcount()
Clifford Wolf
2014-10-15
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Updated lexers & parsers to include prefixes
William Speirs
2014-10-15
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Added make_temp_{file,dir}() and remove_directory() APIs
Clifford Wolf
2014-10-12
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Added run_command() api to replace system() and popen()
Clifford Wolf
2014-10-12
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Do not the 'z' modifier in format string (another win32 fix)
Clifford Wolf
2014-10-11
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Fixed win32 troubles with f.readsome()
Clifford Wolf
2014-10-11
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Disabled vhdl2verilog command for win32 builds
Clifford Wolf
2014-10-11
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Added format __attribute__ to stringf()
Clifford Wolf
2014-10-10
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Renamed SIZE() to GetSize() because of name collision on Win32
Clifford Wolf
2014-10-10
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namespace Yosys
Clifford Wolf
2014-09-27
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Another $clog2 bugfix
Clifford Wolf
2014-09-08
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Fixed $clog2 (off by one error)
Clifford Wolf
2014-09-06
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Fixed assignment of out-of bounds array element
Clifford Wolf
2014-09-06
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Corrected spelling mistakes found by lintian
Ruben Undheim
2014-09-06
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Removed $bu0 cell type
Clifford Wolf
2014-09-04
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Removed compatbility.{h,cc}: Not using open_memstream/fmemopen anymore
Clifford Wolf
2014-08-23
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Changed frontend-api from FILE to std::istream
Clifford Wolf
2014-08-23
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Added emscripten (emcc) support to build system and some build fixes
Clifford Wolf
2014-08-22
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Added support for non-standard <plugin>:<c_name> DPI syntax
Clifford Wolf
2014-08-22
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