yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Renamed $_INV_ cell type to $_NOT_	Clifford Wolf	2014-08-15
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*	Fixed bug in "read_verilog -ignore_redef"	Clifford Wolf	2014-08-15
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*	Added RTLIL::SigSpec::to_sigbit_map()	Clifford Wolf	2014-08-14
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*	Changed the AST genWidthRTLIL subst interface to use a std::map	Clifford Wolf	2014-08-14
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*	Fixed line numbers when using here-doc macros	Clifford Wolf	2014-08-14
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*	Fixed handling of task outputs	Clifford Wolf	2014-08-14
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*	Added module->ports	Clifford Wolf	2014-08-14
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*	Added support for non-standard """ macro bodies	Clifford Wolf	2014-08-13
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*	Fixed building verific bindings	Clifford Wolf	2014-08-12
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*	Also allow "module foobar(input foo, output bar, ...);" syntax	Clifford Wolf	2014-08-07
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*	Added AST_MULTIRANGE (arrays with more than 1 dimension)	Clifford Wolf	2014-08-06
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*	Improved scope resolution of local regs in Verilog+AST frontend	Clifford Wolf	2014-08-05
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*	Fixed AST handling of variables declared inside a functions main block	Clifford Wolf	2014-08-05
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*	Added support for non-standard "module mod_name(...);" syntax	Clifford Wolf	2014-08-04
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*	More bugfixes related to new RTLIL::IdString	Clifford Wolf	2014-08-02
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*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02
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*	Preparations for RTLIL::IdString redesign: cleanup of existing code	Clifford Wolf	2014-08-02
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*	Replaced sha1 implementation	Clifford Wolf	2014-08-01
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*	Fixed build of verific bindings	Clifford Wolf	2014-07-31
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*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31
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*	Added module->design and cell->module, wire->module pointers	Clifford Wolf	2014-07-31
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*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31
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*	Fixed counting verilog line numbers for "// synopsys translate_off" sections	Clifford Wolf	2014-07-30
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*	Fixed Verilog pre-processor for files with no trailing newline	Clifford Wolf	2014-07-29
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*	Added $shift and $shiftx cell types (needed for correct part select behavior)	Clifford Wolf	2014-07-29
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*	Removed left over debug code	Clifford Wolf	2014-07-28
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*	Fixed part selects of parameters	Clifford Wolf	2014-07-28
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*	Set results of out-of-bounds static bit/part select to undef	Clifford Wolf	2014-07-28
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*	Fixed RTLIL code generator for part select of parameter	Clifford Wolf	2014-07-28
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*	Fixed width detection for part selects	Clifford Wolf	2014-07-28
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*	Added support for "upto" wires to Verilog front- and back-end	Clifford Wolf	2014-07-28
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*	Added wire->upto flag for signals such as "wire [0:7] x;"	Clifford Wolf	2014-07-28
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*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28
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*	Fixed signdness detection of expressions with bit- and part-selects	Clifford Wolf	2014-07-28
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*	Added proper Design->addModule interface	Clifford Wolf	2014-07-27
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*	Fixed verific bindings for new RTLIL api	Clifford Wolf	2014-07-27
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*	Fixed ilang parser for new RTLIL API	Clifford Wolf	2014-07-27
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*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27
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*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27
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*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27
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*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26
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*	Added RTLIL::Cell::has(portname)	Clifford Wolf	2014-07-26
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*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26
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*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26
\| \| \| \| \| \| \| \| \|	git grep -l 'connections_' \| xargs sed -i -r -e ' s/(->\|\.)connections_\["([^"])"\] = (.);/\1set("\2", \3);/g; s/(->\|\.)connections_\["([^"])"\]/\1get("\2")/g; s/(->\|\.)connections_.at$"([^"])"$/\1get("\2")/g; s/(->\|\.)connections_.push_back/\1connect/g; s/(->\|\.)connections_/\1connections()/g;'
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26
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*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25
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*	Fixed two memory leaks in ast simplify	Clifford Wolf	2014-07-25
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*	Updated verific build/test instructions	Clifford Wolf	2014-07-25
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*	Replaced more old SigChunk programming patterns	Clifford Wolf	2014-07-24
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*	Added "make PRETTY=1"	Clifford Wolf	2014-07-24
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