| Commit message (Expand) | Author | Age |
|---|
| * | Added support for non-standard """ macro bodies | Clifford Wolf | 2014-08-13 |
| * | Fixed building verific bindings | Clifford Wolf | 2014-08-12 |
| * | Also allow "module foobar(input foo, output bar, ...);" syntax | Clifford Wolf | 2014-08-07 |
| * | Added AST_MULTIRANGE (arrays with more than 1 dimension) | Clifford Wolf | 2014-08-06 |
| * | Improved scope resolution of local regs in Verilog+AST frontend | Clifford Wolf | 2014-08-05 |
| * | Fixed AST handling of variables declared inside a functions main block | Clifford Wolf | 2014-08-05 |
| * | Added support for non-standard "module mod_name(...);" syntax | Clifford Wolf | 2014-08-04 |
| * | More bugfixes related to new RTLIL::IdString | Clifford Wolf | 2014-08-02 |
| * | More cleanups related to RTLIL::IdString usage | Clifford Wolf | 2014-08-02 |
| * | Preparations for RTLIL::IdString redesign: cleanup of existing code | Clifford Wolf | 2014-08-02 |
| * | Replaced sha1 implementation | Clifford Wolf | 2014-08-01 |
| * | Fixed build of verific bindings | Clifford Wolf | 2014-07-31 |
| * | Renamed port access function on RTLIL::Cell, added param access functions | Clifford Wolf | 2014-07-31 |
| * | Added module->design and cell->module, wire->module pointers | Clifford Wolf | 2014-07-31 |
| * | Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace | Clifford Wolf | 2014-07-31 |
| * | Fixed counting verilog line numbers for "// synopsys translate_off" sections | Clifford Wolf | 2014-07-30 |
| * | Fixed Verilog pre-processor for files with no trailing newline | Clifford Wolf | 2014-07-29 |
| * | Added $shift and $shiftx cell types (needed for correct part select behavior) | Clifford Wolf | 2014-07-29 |
| * | Removed left over debug code | Clifford Wolf | 2014-07-28 |
| * | Fixed part selects of parameters | Clifford Wolf | 2014-07-28 |
| * | Set results of out-of-bounds static bit/part select to undef | Clifford Wolf | 2014-07-28 |
| * | Fixed RTLIL code generator for part select of parameter | Clifford Wolf | 2014-07-28 |
| * | Fixed width detection for part selects | Clifford Wolf | 2014-07-28 |
| * | Added support for "upto" wires to Verilog front- and back-end | Clifford Wolf | 2014-07-28 |
| * | Added wire->upto flag for signals such as "wire [0:7] x;" | Clifford Wolf | 2014-07-28 |
| * | Using log_assert() instead of assert() | Clifford Wolf | 2014-07-28 |
| * | Fixed signdness detection of expressions with bit- and part-selects | Clifford Wolf | 2014-07-28 |
| * | Added proper Design->addModule interface | Clifford Wolf | 2014-07-27 |
| * | Fixed verific bindings for new RTLIL api | Clifford Wolf | 2014-07-27 |
| * | Fixed ilang parser for new RTLIL API | Clifford Wolf | 2014-07-27 |
| * | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 |
| * | Refactoring: Renamed RTLIL::Module::cells to cells_ | Clifford Wolf | 2014-07-27 |
| * | Refactoring: Renamed RTLIL::Module::wires to wires_ | Clifford Wolf | 2014-07-27 |
| * | Changed a lot of code to the new RTLIL::Wire constructors | Clifford Wolf | 2014-07-26 |
| * | Added RTLIL::Cell::has(portname) | Clifford Wolf | 2014-07-26 |
| * | Manual fixes for new cell connections API | Clifford Wolf | 2014-07-26 |
| * | Changed users of cell->connections_ to the new API (sed command) | Clifford Wolf | 2014-07-26 |
| * | Renamed RTLIL::{Module,Cell}::connections to connections_ | Clifford Wolf | 2014-07-26 |
| * | Use only module->addCell() and module->remove() to create and delete cells | Clifford Wolf | 2014-07-25 |
| * | Fixed two memory leaks in ast simplify | Clifford Wolf | 2014-07-25 |
| * | Updated verific build/test instructions | Clifford Wolf | 2014-07-25 |
| * | Replaced more old SigChunk programming patterns | Clifford Wolf | 2014-07-24 |
| * | Added "make PRETTY=1" | Clifford Wolf | 2014-07-24 |
| * | Various fixes in Verific frontend for new RTLIL API | Clifford Wolf | 2014-07-23 |
| * | Various small fixes (from gcc compiler warnings) | Clifford Wolf | 2014-07-23 |
| * | Removed RTLIL::SigSpec::optimize() | Clifford Wolf | 2014-07-23 |
| * | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3 | Clifford Wolf | 2014-07-23 |
| * | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3 | Clifford Wolf | 2014-07-23 |
| * | SigSpec refactoring: More cleanups of old SigSpec use pattern | Clifford Wolf | 2014-07-22 |
| * | SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created... | Clifford Wolf | 2014-07-22 |
