yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Added Verilog support for "`default_nettype none"	Clifford Wolf	2014-02-17
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*	Added a warning note about error reporting to read_verilog help message	Clifford Wolf	2014-02-16
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*	Improved support for constant functions	Clifford Wolf	2014-02-16
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*	Added ff and latch support to read_liberty	Clifford Wolf	2014-02-15
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*	Bugfix in expression parser of read_liberty	Clifford Wolf	2014-02-15
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*	Correctly convert constants to RTLIL (fixed undef handling)	Clifford Wolf	2014-02-15
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*	Added liberty frontend	Clifford Wolf	2014-02-15
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*	Be more conservative with new const-function code	Clifford Wolf	2014-02-14
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*	Added support for FOR loops in function calls in parameters	Clifford Wolf	2014-02-14
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*	Created basic support for function calls in parameter values	Clifford Wolf	2014-02-14
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*	Implemented read_verilog -defer	Clifford Wolf	2014-02-13
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*	Added support for functions returning integer	Clifford Wolf	2014-02-12
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*	renamed ilang "scope error" to "ilang error"	Clifford Wolf	2014-02-11
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*	Improved ilang parser error messages	Clifford Wolf	2014-02-09
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*	Fixed gcc compiler warnings with release build	Clifford Wolf	2014-02-06
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*	Added read_verilog -setattr	Clifford Wolf	2014-02-05
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*	Fixed bug in sequential sat proofs and improved handling of asserts	Clifford Wolf	2014-02-04
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*	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	Clifford Wolf	2014-02-03
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*	Added support for blanks after -I and -D in read_verilog	Clifford Wolf	2014-02-02
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*	Fixed comment/eol parsing in ilang frontend	Clifford Wolf	2014-02-01
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*	Added constant size expression support of sized constants	Clifford Wolf	2014-02-01
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*	Bugfix in name resolution with generate blocks	Clifford Wolf	2014-01-30
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*	Added read_verilog -icells option	Clifford Wolf	2014-01-29
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*	Fixed handling of unsized constants in verilog frontend	Clifford Wolf	2014-01-24
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*	Fixed algorithmic complexity of AST simplification of long expressions	Clifford Wolf	2014-01-20
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*	Added $assert cell	Clifford Wolf	2014-01-19
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*	Added Verilog parser support for asserts	Clifford Wolf	2014-01-19
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*	Fixed parsing of verilog macros at end of line	Clifford Wolf	2014-01-18
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*	Added verilog_defaults command	Clifford Wolf	2014-01-17
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*	Fixed typo in frontends/ast/simplify.cc	Clifford Wolf	2014-01-12
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*	Added updating of RTLIL::autoidx to ilang frontend	Clifford Wolf	2014-01-03
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*	Added correct handling of $memwr priority	Clifford Wolf	2014-01-03
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*	Fixed a stupid access after delete bug	Clifford Wolf	2013-12-29
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*	Fixed parsing of non-arg macro calls followed by "("	Clifford Wolf	2013-12-27
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*	Fixed parsing of macros with no arguments and expansion text starting with "("	Clifford Wolf	2013-12-27
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*	Added support for non-const === and !== (for miter circuits)	Clifford Wolf	2013-12-27
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*	Added proper === and !== support in constant expressions	Clifford Wolf	2013-12-27
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*	Added elsif preproc support	Clifford Wolf	2013-12-18
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*	Added support for macro arguments	Clifford Wolf	2013-12-18
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*	Keep strings as strings in const ternary and concat	Clifford Wolf	2013-12-05
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*	Added const folding support for $signed and $unsigned	Clifford Wolf	2013-12-05
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*	Added AstNode::mkconst_str API	Clifford Wolf	2013-12-05
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*	Fixed generate-for (and disabled double warning for auto-wire)	Clifford Wolf	2013-12-04
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*	Added support for $clog2 system function	Clifford Wolf	2013-12-04
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*	Various improvements in support for generate statements	Clifford Wolf	2013-12-04
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*	Replaced signed_parameters API with CONST_FLAG_SIGNED	Clifford Wolf	2013-12-04
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*	Replaced RTLIL::Const::str with generic decoder method	Clifford Wolf	2013-12-04
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*	Added support for local regs in named blocks	Clifford Wolf	2013-12-04
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*	Fixed temp net name generation in rtlil process generator for abbreviated ↵	Clifford Wolf	2013-11-28
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*	Added "src" attribute to processes	Clifford Wolf	2013-11-28
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