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* Added AST_INITIAL checks for $finish and $displayClifford Wolf2015-09-18
* Initial implementation of $display()Andrew Zonenberg2015-09-18
* Initial implementation of $finish()Andrew Zonenberg2015-09-18
* gcc-4.6 build fixesClifford Wolf2015-09-01
* Fixed handling of memory read without addressClifford Wolf2015-08-22
* Small corrections to const2ast warning messagesClifford Wolf2015-08-17
* Check base-n literals only contain valid digitsFlorian Zeitz2015-08-17
* Warn on literals exceeding the specified bit widthFlorian Zeitz2015-08-17
* Another block of spelling fixesLarry Doolittle2015-08-14
* Keep gcc from complaining about uninitialized variablesLarry Doolittle2015-08-14
* Re-created command-reference-manual.tex, copied some doc fixes to online helpClifford Wolf2015-08-14
* Spell check (by Larry Doolittle)Clifford Wolf2015-08-14
* Adjust makefiles to work with out-of-tree buildsClifford Wolf2015-08-12
* Fixed handling of [a-fxz?] in decimal constantsClifford Wolf2015-08-11
* Add -noautowire option to verilog frontendMarcus Comstedt2015-08-01
* Added WORDS parameter to $meminitClifford Wolf2015-07-31
* Fixed nested mem2regClifford Wolf2015-07-29
* Fixed trailing whitespacesClifford Wolf2015-07-02
* Fixed handling of parameters with reversed rangeClifford Wolf2015-06-08
* Fixed signedness of genvar expressionsClifford Wolf2015-05-29
* Improvements in BLIF front-endClifford Wolf2015-05-24
* bugfix in blif front-endClifford Wolf2015-05-18
* Improved .latch support in BLIF front-endClifford Wolf2015-05-17
* Added read_blif commandClifford Wolf2015-05-17
* Generalized blifparse APIClifford Wolf2015-05-17
* abc/blifparse files reorganizationClifford Wolf2015-05-17
* Verific build fixesClifford Wolf2015-05-17
* Verilog front-end: define `BLACKBOX in -lib modeClifford Wolf2015-04-19
* Ignore celldefine directive in verilog front-endClifford Wolf2015-03-25
* Const-fold parameter defs on-demand in AstNode::detectSignWidthWorker()Clifford Wolf2015-03-01
* Added non-std verilog assume() statementClifford Wolf2015-02-26
* Added deep recursion warning to AST simplifyClifford Wolf2015-02-20
* Parser support for complex delay expressionsClifford Wolf2015-02-20
* YosysJS stuffClifford Wolf2015-02-19
* Convert floating point cell parameters to stringsClifford Wolf2015-02-18
* Various fixes for memories with offsetsClifford Wolf2015-02-14
* Added "read_verilog -nomeminit" and "nomeminit" attributeClifford Wolf2015-02-14
* Creating $meminit cells in verilog front-endClifford Wolf2015-02-14
* Fixed handling of "//" in filenames in verilog pre-processorClifford Wolf2015-02-14
* Added AstNode::simplify() recursion counterClifford Wolf2015-02-13
* Improved read_verilog support for empty behavioral statementsClifford Wolf2015-02-10
* Ignore explicit assignments to constants in HDL codeClifford Wolf2015-02-08
* Fixed a bug with autowire bit sizeClifford Wolf2015-02-08
* Added ENABLE_NDEBUG makefile optionsClifford Wolf2015-01-24
* Ignoring more system task and functionsClifford Wolf2015-01-15
* Fixed handling of "input foo; reg [0:0] foo;"Clifford Wolf2015-01-15
* Consolidate "Blocking assignment to memory.." msgs for the same lineClifford Wolf2015-01-15
* Enable bison to be customizedFabio Utzig2015-01-08
* Define YOSYS and SYNTHESIS in preprocClifford Wolf2015-01-02
* Fixed memory->start_offset handlingClifford Wolf2015-01-01