yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Added AST_INITIAL checks for $finish and $display	Clifford Wolf	2015-09-18
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*	Initial implementation of $display()	Andrew Zonenberg	2015-09-18
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*	Initial implementation of $finish()	Andrew Zonenberg	2015-09-18
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*	gcc-4.6 build fixes	Clifford Wolf	2015-09-01
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*	Fixed handling of memory read without address	Clifford Wolf	2015-08-22
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*	Small corrections to const2ast warning messages	Clifford Wolf	2015-08-17
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*	Check base-n literals only contain valid digits	Florian Zeitz	2015-08-17
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*	Warn on literals exceeding the specified bit width	Florian Zeitz	2015-08-17
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*	Another block of spelling fixes	Larry Doolittle	2015-08-14
\| \| \| \|	Smaller this time
*	Keep gcc from complaining about uninitialized variables	Larry Doolittle	2015-08-14
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*	Re-created command-reference-manual.tex, copied some doc fixes to online help	Clifford Wolf	2015-08-14
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*	Spell check (by Larry Doolittle)	Clifford Wolf	2015-08-14
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*	Adjust makefiles to work with out-of-tree builds	Clifford Wolf	2015-08-12
\| \| \| \|	This is based on work done by Larry Doolittle
*	Fixed handling of [a-fxz?] in decimal constants	Clifford Wolf	2015-08-11
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*	Add -noautowire option to verilog frontend	Marcus Comstedt	2015-08-01
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*	Added WORDS parameter to $meminit	Clifford Wolf	2015-07-31
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*	Fixed nested mem2reg	Clifford Wolf	2015-07-29
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*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02
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*	Fixed handling of parameters with reversed range	Clifford Wolf	2015-06-08
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*	Fixed signedness of genvar expressions	Clifford Wolf	2015-05-29
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*	Improvements in BLIF front-end	Clifford Wolf	2015-05-24
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*	bugfix in blif front-end	Clifford Wolf	2015-05-18
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*	Improved .latch support in BLIF front-end	Clifford Wolf	2015-05-17
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*	Added read_blif command	Clifford Wolf	2015-05-17
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*	Generalized blifparse API	Clifford Wolf	2015-05-17
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*	abc/blifparse files reorganization	Clifford Wolf	2015-05-17
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*	Verific build fixes	Clifford Wolf	2015-05-17
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*	Verilog front-end: define `BLACKBOX in -lib mode	Clifford Wolf	2015-04-19
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*	Ignore celldefine directive in verilog front-end	Clifford Wolf	2015-03-25
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*	Const-fold parameter defs on-demand in AstNode::detectSignWidthWorker()	Clifford Wolf	2015-03-01
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*	Added non-std verilog assume() statement	Clifford Wolf	2015-02-26
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*	Added deep recursion warning to AST simplify	Clifford Wolf	2015-02-20
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*	Parser support for complex delay expressions	Clifford Wolf	2015-02-20
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*	YosysJS stuff	Clifford Wolf	2015-02-19
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*	Convert floating point cell parameters to strings	Clifford Wolf	2015-02-18
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*	Various fixes for memories with offsets	Clifford Wolf	2015-02-14
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*	Added "read_verilog -nomeminit" and "nomeminit" attribute	Clifford Wolf	2015-02-14
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*	Creating $meminit cells in verilog front-end	Clifford Wolf	2015-02-14
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*	Fixed handling of "//" in filenames in verilog pre-processor	Clifford Wolf	2015-02-14
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*	Added AstNode::simplify() recursion counter	Clifford Wolf	2015-02-13
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*	Improved read_verilog support for empty behavioral statements	Clifford Wolf	2015-02-10
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*	Ignore explicit assignments to constants in HDL code	Clifford Wolf	2015-02-08
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*	Fixed a bug with autowire bit size	Clifford Wolf	2015-02-08
\| \| \| \|	(removed leftover from when we tried to auto-size the wires)
*	Added ENABLE_NDEBUG makefile options	Clifford Wolf	2015-01-24
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*	Ignoring more system task and functions	Clifford Wolf	2015-01-15
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*	Fixed handling of "input foo; reg [0:0] foo;"	Clifford Wolf	2015-01-15
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*	Consolidate "Blocking assignment to memory.." msgs for the same line	Clifford Wolf	2015-01-15
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*	Enable bison to be customized	Fabio Utzig	2015-01-08
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*	Define YOSYS and SYNTHESIS in preproc	Clifford Wolf	2015-01-02
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*	Fixed memory->start_offset handling	Clifford Wolf	2015-01-01
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