yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
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*	Print "SystemVerilog" in "read_verilog -sv" log messages	Clifford Wolf	2014-10-16
*	Fixed handling of invalid array access in mem2reg code	Clifford Wolf	2014-10-16
*	Updated .gitignore file for ilang and verilog frontends	Clifford Wolf	2014-10-15
*	Replaced readsome() with read() and gcount()	Clifford Wolf	2014-10-15
*	Updated lexers & parsers to include prefixes	William Speirs	2014-10-15
*	Added make_temp_{file,dir}() and remove_directory() APIs	Clifford Wolf	2014-10-12
*	Added run_command() api to replace system() and popen()	Clifford Wolf	2014-10-12
*	Do not the 'z' modifier in format string (another win32 fix)	Clifford Wolf	2014-10-11
*	Fixed win32 troubles with f.readsome()	Clifford Wolf	2014-10-11
*	Disabled vhdl2verilog command for win32 builds	Clifford Wolf	2014-10-11
*	Added format __attribute__ to stringf()	Clifford Wolf	2014-10-10
*	Renamed SIZE() to GetSize() because of name collision on Win32	Clifford Wolf	2014-10-10
*	namespace Yosys	Clifford Wolf	2014-09-27
*	Another $clog2 bugfix	Clifford Wolf	2014-09-08
*	Fixed $clog2 (off by one error)	Clifford Wolf	2014-09-06
*	Fixed assignment of out-of bounds array element	Clifford Wolf	2014-09-06
*	Corrected spelling mistakes found by lintian	Ruben Undheim	2014-09-06
*	Removed $bu0 cell type	Clifford Wolf	2014-09-04
*	Removed compatbility.{h,cc}: Not using open_memstream/fmemopen anymore	Clifford Wolf	2014-08-23
*	Changed frontend-api from FILE to std::istream	Clifford Wolf	2014-08-23
*	Added emscripten (emcc) support to build system and some build fixes	Clifford Wolf	2014-08-22
*	Added support for non-standard <plugin>:<c_name> DPI syntax	Clifford Wolf	2014-08-22
*	Archibald Rust and Clifford Wolf: ffi-based dpi_call()	Clifford Wolf	2014-08-22
*	Fixed small memory leak in ast simplify	Clifford Wolf	2014-08-21
*	Added support for DPI function with different names in C and Verilog	Clifford Wolf	2014-08-21
*	Added AstNode::asInt()	Clifford Wolf	2014-08-21
*	Fixed memory leak in DPI function calls	Clifford Wolf	2014-08-21
*	Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)	Clifford Wolf	2014-08-21
*	Added support for global tasks and functions	Clifford Wolf	2014-08-21
*	Added "via_celltype" attribute on task/func	Clifford Wolf	2014-08-18
*	Added const folding of AST_CASE to AST simplifier	Clifford Wolf	2014-08-18
*	Improved AST ProcessGenerator performance	Clifford Wolf	2014-08-17
*	Use stackmap<> in AST ProcessGenerator	Clifford Wolf	2014-08-17
*	Added module->uniquify()	Clifford Wolf	2014-08-16
*	AST ProcessGenerator: replaced subst__{from,to} with subst__map	Clifford Wolf	2014-08-16
*	Renamed $_INV_ cell type to $_NOT_	Clifford Wolf	2014-08-15
*	Fixed bug in "read_verilog -ignore_redef"	Clifford Wolf	2014-08-15
*	Added RTLIL::SigSpec::to_sigbit_map()	Clifford Wolf	2014-08-14
*	Changed the AST genWidthRTLIL subst interface to use a std::map	Clifford Wolf	2014-08-14
*	Fixed line numbers when using here-doc macros	Clifford Wolf	2014-08-14
*	Fixed handling of task outputs	Clifford Wolf	2014-08-14
*	Added module->ports	Clifford Wolf	2014-08-14
*	Added support for non-standard """ macro bodies	Clifford Wolf	2014-08-13
*	Fixed building verific bindings	Clifford Wolf	2014-08-12
*	Also allow "module foobar(input foo, output bar, ...);" syntax	Clifford Wolf	2014-08-07
*	Added AST_MULTIRANGE (arrays with more than 1 dimension)	Clifford Wolf	2014-08-06
*	Improved scope resolution of local regs in Verilog+AST frontend	Clifford Wolf	2014-08-05
*	Fixed AST handling of variables declared inside a functions main block	Clifford Wolf	2014-08-05
*	Added support for non-standard "module mod_name(...);" syntax	Clifford Wolf	2014-08-04
*	More bugfixes related to new RTLIL::IdString	Clifford Wolf	2014-08-02