yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Verific build fixes	Clifford Wolf	2015-05-17
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*	Verilog front-end: define `BLACKBOX in -lib mode	Clifford Wolf	2015-04-19
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*	Ignore celldefine directive in verilog front-end	Clifford Wolf	2015-03-25
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*	Const-fold parameter defs on-demand in AstNode::detectSignWidthWorker()	Clifford Wolf	2015-03-01
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*	Added non-std verilog assume() statement	Clifford Wolf	2015-02-26
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*	Added deep recursion warning to AST simplify	Clifford Wolf	2015-02-20
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*	Parser support for complex delay expressions	Clifford Wolf	2015-02-20
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*	YosysJS stuff	Clifford Wolf	2015-02-19
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*	Convert floating point cell parameters to strings	Clifford Wolf	2015-02-18
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*	Various fixes for memories with offsets	Clifford Wolf	2015-02-14
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*	Added "read_verilog -nomeminit" and "nomeminit" attribute	Clifford Wolf	2015-02-14
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*	Creating $meminit cells in verilog front-end	Clifford Wolf	2015-02-14
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*	Fixed handling of "//" in filenames in verilog pre-processor	Clifford Wolf	2015-02-14
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*	Added AstNode::simplify() recursion counter	Clifford Wolf	2015-02-13
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*	Improved read_verilog support for empty behavioral statements	Clifford Wolf	2015-02-10
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*	Ignore explicit assignments to constants in HDL code	Clifford Wolf	2015-02-08
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*	Fixed a bug with autowire bit size	Clifford Wolf	2015-02-08
\| \| \| \|	(removed leftover from when we tried to auto-size the wires)
*	Added ENABLE_NDEBUG makefile options	Clifford Wolf	2015-01-24
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*	Ignoring more system task and functions	Clifford Wolf	2015-01-15
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*	Fixed handling of "input foo; reg [0:0] foo;"	Clifford Wolf	2015-01-15
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*	Consolidate "Blocking assignment to memory.." msgs for the same line	Clifford Wolf	2015-01-15
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*	Enable bison to be customized	Fabio Utzig	2015-01-08
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*	Define YOSYS and SYNTHESIS in preproc	Clifford Wolf	2015-01-02
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*	Fixed memory->start_offset handling	Clifford Wolf	2015-01-01
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*	Added global yosys_celltypes	Clifford Wolf	2014-12-29
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*	dict/pool changes in ast	Clifford Wolf	2014-12-29
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*	Changed more code to dict<> and pool<>	Clifford Wolf	2014-12-28
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*	Improved some warning messages	Clifford Wolf	2014-12-27
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*	Fixed mem2reg warning message	Clifford Wolf	2014-12-27
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*	Added Yosys::{dict,nodict,vector} container types	Clifford Wolf	2014-12-26
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*	Renamed extend() to extend_xx(), changed most users to extend_u0()	Clifford Wolf	2014-12-24
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*	Fixed supply0/supply1 with many wires	Clifford Wolf	2014-12-11
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*	Fixed minor bug in parsing delays	Clifford Wolf	2014-11-24
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*	Fixed two minor bugs in constant parsing	Clifford Wolf	2014-11-24
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*	Added warning for use of 'z' constants in HDL	Clifford Wolf	2014-11-14
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*	Fixed parsing of nested verilog concatenation and replicate	Clifford Wolf	2014-11-12
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*	Added log_warning() API	Clifford Wolf	2014-11-09
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*	Added "ENABLE_PLUGINS := 0" to verific amd64 build instructions	Clifford Wolf	2014-11-08
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*	Fixed parsing of "module mymod #( parameter foo = 1, bar = 2 ..."	Clifford Wolf	2014-10-30
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*	AST simplifier: optimize constant AST_CASE nodes before recursively descending	Clifford Wolf	2014-10-29
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*	Added support for task and function args in parentheses	Clifford Wolf	2014-10-27
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*	Improvements in $readmem[bh] implementation	Clifford Wolf	2014-10-26
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*	Added support for $readmemh/$readmemb	Clifford Wolf	2014-10-26
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*	Fixed constant "cond ? string1 : string2" with strings of different size	Clifford Wolf	2014-10-25
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*	Re-introduced Yosys::readsome() helper function	Clifford Wolf	2014-10-23
\| \| \| \|	(f.read() + f.gcount() made problems with lines > 16kB)
*	minor indenting corrections	Clifford Wolf	2014-10-19
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*	Builds on Mac 10.9.2 with LLVM 3.5.	Parviz Palangpour	2014-10-19
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*	Fixed various VS warnings	Clifford Wolf	2014-10-18
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*	Header changes so it will compile on VS	William Speirs	2014-10-17
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*	Wrapped math in int constructor	William Speirs	2014-10-17
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