yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25
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*	Fixed two memory leaks in ast simplify	Clifford Wolf	2014-07-25
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*	Updated verific build/test instructions	Clifford Wolf	2014-07-25
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*	Replaced more old SigChunk programming patterns	Clifford Wolf	2014-07-24
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*	Added "make PRETTY=1"	Clifford Wolf	2014-07-24
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*	Various fixes in Verific frontend for new RTLIL API	Clifford Wolf	2014-07-23
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*	Various small fixes (from gcc compiler warnings)	Clifford Wolf	2014-07-23
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*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23
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*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	Clifford Wolf	2014-07-23
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*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3	Clifford Wolf	2014-07-23
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*	SigSpec refactoring: More cleanups of old SigSpec use pattern	Clifford Wolf	2014-07-22
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*	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, ↵	Clifford Wolf	2014-07-22
\| \| \| \|	created interim RTLIL::SigSpec::chunks_rw()
*	SigSpec refactoring: change RTLIL::SigSpec::size() to be read-only	Clifford Wolf	2014-07-22
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*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22
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*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22
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*	Fixed ilang parsing of process attributes	Clifford Wolf	2014-07-22
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*	Fixed make rules for ilang parser	Clifford Wolf	2014-07-22
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*	Added "autoidx" statement to ilang file format	Clifford Wolf	2014-07-21
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*	Replaced depricated NEW_WIRE macro with module->addWire() calls	Clifford Wolf	2014-07-21
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*	Removed deprecated module->new_wire()	Clifford Wolf	2014-07-21
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*	Implemented dynamic bit-/part-select for memory writes	Clifford Wolf	2014-07-17
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*	Added support for bit/part select to mem2reg rewriter	Clifford Wolf	2014-07-17
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*	Added support for constant bit- or part-select for memory writes	Clifford Wolf	2014-07-17
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*	Added "inout" ports support to read_liberty	Clifford Wolf	2014-07-16
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*	Set blackbox attribute in "read_liberty -lib"	Clifford Wolf	2014-07-16
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*	Fixed spelling of "direction" in read_liberty messages	Clifford Wolf	2014-07-16
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*	changes in verilog frontend for new $mem/$memwr WR_EN interface	Clifford Wolf	2014-07-16
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*	Added passing of various options to vhdl2verilog	Clifford Wolf	2014-07-12
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*	Fixed processing of initial values for block-local variables	Clifford Wolf	2014-07-11
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*	fixed parsing of constant with comment between size and value	Clifford Wolf	2014-07-02
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*	Fixed handling of mixed real/int ternary expressions	Clifford Wolf	2014-06-25
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*	More found_real-related fixes to AstNode::detectSignWidthWorker	Clifford Wolf	2014-06-24
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*	fixed signdness detection for expressions with reals	Clifford Wolf	2014-06-21
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*	Added AstNode::MEM2REG_FL_CMPLX_LHS	Clifford Wolf	2014-06-17
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*	Improved handling of relational op of real values	Clifford Wolf	2014-06-17
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*	Improved ternary support for real values	Clifford Wolf	2014-06-16
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*	Use undef (x/z vs. NaN) rules for real values from IEEE Std 1800-2012	Clifford Wolf	2014-06-16
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*	Fixed parsing of TOK_INTEGER (implies TOK_SIGNED)	Clifford Wolf	2014-06-16
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*	Added found_real feature to AstNode::detectSignWidth	Clifford Wolf	2014-06-16
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*	Improved AstNode::realAsConst for large numbers	Clifford Wolf	2014-06-15
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*	Improved parsing of large integer constants	Clifford Wolf	2014-06-15
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*	Improved AstNode::asReal for large integers	Clifford Wolf	2014-06-15
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*	improved (fixed) conversion of real values to bit vectors	Clifford Wolf	2014-06-14
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*	Fixed relational operators for const real expressions	Clifford Wolf	2014-06-14
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*	Added support for math functions	Clifford Wolf	2014-06-14
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*	Added handling of real-valued parameters/localparams	Clifford Wolf	2014-06-14
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*	Implemented more real arithmetic	Clifford Wolf	2014-06-14
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*	Implemented basic real arithmetic	Clifford Wolf	2014-06-14
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*	Added real->int convertion in ast genrtlil	Clifford Wolf	2014-06-14
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*	Added Verilog lexer and parser support for real values	Clifford Wolf	2014-06-13
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