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* Fixed ilang parser for new RTLIL APIClifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-26
* Added RTLIL::Cell::has(portname)Clifford Wolf2014-07-26
* Manual fixes for new cell connections APIClifford Wolf2014-07-26
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-25
* Fixed two memory leaks in ast simplifyClifford Wolf2014-07-25
* Updated verific build/test instructionsClifford Wolf2014-07-25
* Replaced more old SigChunk programming patternsClifford Wolf2014-07-24
* Added "make PRETTY=1"Clifford Wolf2014-07-24
* Various fixes in Verific frontend for new RTLIL APIClifford Wolf2014-07-23
* Various small fixes (from gcc compiler warnings)Clifford Wolf2014-07-23
* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-23
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3Clifford Wolf2014-07-23
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3Clifford Wolf2014-07-23
* SigSpec refactoring: More cleanups of old SigSpec use patternClifford Wolf2014-07-22
* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...Clifford Wolf2014-07-22
* SigSpec refactoring: change RTLIL::SigSpec::size() to be read-onlyClifford Wolf2014-07-22
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
* Fixed ilang parsing of process attributesClifford Wolf2014-07-22
* Fixed make rules for ilang parserClifford Wolf2014-07-22
* Added "autoidx" statement to ilang file formatClifford Wolf2014-07-21
* Replaced depricated NEW_WIRE macro with module->addWire() callsClifford Wolf2014-07-21
* Removed deprecated module->new_wire()Clifford Wolf2014-07-21
* Implemented dynamic bit-/part-select for memory writesClifford Wolf2014-07-17
* Added support for bit/part select to mem2reg rewriterClifford Wolf2014-07-17
* Added support for constant bit- or part-select for memory writesClifford Wolf2014-07-17
* Added "inout" ports support to read_libertyClifford Wolf2014-07-16
* Set blackbox attribute in "read_liberty -lib"Clifford Wolf2014-07-16
* Fixed spelling of "direction" in read_liberty messagesClifford Wolf2014-07-16
* changes in verilog frontend for new $mem/$memwr WR_EN interfaceClifford Wolf2014-07-16
* Added passing of various options to vhdl2verilogClifford Wolf2014-07-12
* Fixed processing of initial values for block-local variablesClifford Wolf2014-07-11
* fixed parsing of constant with comment between size and valueClifford Wolf2014-07-02
* Fixed handling of mixed real/int ternary expressionsClifford Wolf2014-06-25
* More found_real-related fixes to AstNode::detectSignWidthWorkerClifford Wolf2014-06-24
* fixed signdness detection for expressions with realsClifford Wolf2014-06-21
* Added AstNode::MEM2REG_FL_CMPLX_LHSClifford Wolf2014-06-17
* Improved handling of relational op of real valuesClifford Wolf2014-06-17
* Improved ternary support for real valuesClifford Wolf2014-06-16
* Use undef (x/z vs. NaN) rules for real values from IEEE Std 1800-2012Clifford Wolf2014-06-16
* Fixed parsing of TOK_INTEGER (implies TOK_SIGNED)Clifford Wolf2014-06-16
* Added found_real feature to AstNode::detectSignWidthClifford Wolf2014-06-16
* Improved AstNode::realAsConst for large numbersClifford Wolf2014-06-15
* Improved parsing of large integer constantsClifford Wolf2014-06-15