yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Fixed propagation of width hints for $signed() and $unsigned()	Clifford Wolf	2013-11-06
*	Additional fixes for undef propagation in concat and replicate ops	Clifford Wolf	2013-11-06
*	Improved width extension with regard to undef propagation	Clifford Wolf	2013-11-06
*	Another fix for early width and sign detection in ast simplifier	Clifford Wolf	2013-11-04
*	Fixed const folding of ternary operator	Clifford Wolf	2013-11-04
*	Use proper bit width ans sign extension for const folding	Clifford Wolf	2013-11-04
*	Fixes for early width and sign detection in ast simplifier	Clifford Wolf	2013-11-04
*	further improved early width and sign detection in ast simplifier	Clifford Wolf	2013-11-04
*	Fixed detectSignWidthWorker (ast frontend) for AST_CONCAT	Clifford Wolf	2013-11-03
*	Behavior should be identical now to rev. 0b4a64ac6adbd6 (next: testing before...	Clifford Wolf	2013-11-02
*	Various ast changes for early expression width detection (prep for constfold ...	Clifford Wolf	2013-11-02
*	Fixed handling of boolean attributes (frontends)	Clifford Wolf	2013-10-24
*	Fixed handling of boolean attributes (kernel)	Clifford Wolf	2013-10-24
*	Fixed parsing of value-less attributes in ilang	Clifford Wolf	2013-10-23
*	fixed Verilog parser filename and line numbering issue with include files	Johann Glaser	2013-08-21
*	Added support for include directories with the new '-I' argument of the	Johann Glaser	2013-08-20
*	Added support for notif0/notif1 primitives	Johann Glaser	2013-08-20
*	Fixed width and sign detection for ** operator	Clifford Wolf	2013-08-19
*	Added support for bufif0/bufif1 primitives	Clifford Wolf	2013-08-19
*	Improved ast dumping (ast/verilog frontend)	Clifford Wolf	2013-08-19
*	Added support for "2**n" shifter encoding	Clifford Wolf	2013-08-12
*	Added $div and $mod technology mapping	Clifford Wolf	2013-08-09
*	Added "design" command (-reset, -save, -load)	Clifford Wolf	2013-07-27
*	More fixes in ternary op sign handling	Clifford Wolf	2013-07-12
*	Fixed sign handling in ternary operator	Clifford Wolf	2013-07-12
*	Another vloghammer related bugfix	Clifford Wolf	2013-07-11
*	Fixed sign propagation in bit-wise operators	Clifford Wolf	2013-07-09
*	More fixes in ast expression sign/width handling	Clifford Wolf	2013-07-09
*	Major redesign of expr width/sign detecion (verilog/ast frontend)	Clifford Wolf	2013-07-09
*	Fixed another bug found using vloghammer	Clifford Wolf	2013-07-07
*	Fixed AST_CONSTANT node generation	Clifford Wolf	2013-07-07
*	Added defparam support to Verilog/AST frontend	Clifford Wolf	2013-07-04
*	More fixes for bugs found using xsthammer	Clifford Wolf	2013-06-13
*	Further improved and extended xsthammer	Clifford Wolf	2013-06-11
*	Sign-extension related fixes in SatGen and AST frontend	Clifford Wolf	2013-06-10
*	Fixes and improvements in AST const folding	Clifford Wolf	2013-06-10
*	Enabled AST/Verilog front-end optimizations per default	Clifford Wolf	2013-06-10
*	Added SAT generator and simple sat_solve command	Clifford Wolf	2013-06-07
*	Added log_assert() api	Clifford Wolf	2013-05-24
*	Fixed memory leak in ilang frontend	Clifford Wolf	2013-05-23
*	added option '-Dname[=definition]' to command 'read_verilog'	Johann Glaser	2013-05-19
*	Merge branch 'bugfix'	Clifford Wolf	2013-05-16
\|\
\| *	Fixed synthesis of functions in latched blocks	Clifford Wolf	2013-05-16
* \|	Added support for verilog === operator	Clifford Wolf	2013-05-07
* \|	Fixed handling of positional module parameters	Clifford Wolf	2013-04-26
* \|	Only use sha1 checksums for names of parametric modules when the verbose form...	Clifford Wolf	2013-04-26
* \|	Fixed a bug in AST frontend for cases with non-blocking assigned variables as...	Clifford Wolf	2013-04-13
* \|	Now only use value from "initial" when no matching "always" block is found	Clifford Wolf	2013-03-31
* \|	Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)	Clifford Wolf	2013-03-31
* \|	Implemented proper handling of stub placeholder modules	Clifford Wolf	2013-03-28