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* Removed compatbility.{h,cc}: Not using open_memstream/fmemopen anymoreClifford Wolf2014-08-23
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* Changed frontend-api from FILE to std::istreamClifford Wolf2014-08-23
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* Added emscripten (emcc) support to build system and some build fixesClifford Wolf2014-08-22
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* Added support for non-standard <plugin>:<c_name> DPI syntaxClifford Wolf2014-08-22
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* Archibald Rust and Clifford Wolf: ffi-based dpi_call()Clifford Wolf2014-08-22
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* Fixed small memory leak in ast simplifyClifford Wolf2014-08-21
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* Added support for DPI function with different names in C and VerilogClifford Wolf2014-08-21
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* Added AstNode::asInt()Clifford Wolf2014-08-21
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* Fixed memory leak in DPI function callsClifford Wolf2014-08-21
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* Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)Clifford Wolf2014-08-21
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* Added support for global tasks and functionsClifford Wolf2014-08-21
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* Added "via_celltype" attribute on task/funcClifford Wolf2014-08-18
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* Added const folding of AST_CASE to AST simplifierClifford Wolf2014-08-18
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* Improved AST ProcessGenerator performanceClifford Wolf2014-08-17
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* Use stackmap<> in AST ProcessGeneratorClifford Wolf2014-08-17
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* Added module->uniquify()Clifford Wolf2014-08-16
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* AST ProcessGenerator: replaced subst_*_{from,to} with subst_*_mapClifford Wolf2014-08-16
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* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-15
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* Fixed bug in "read_verilog -ignore_redef"Clifford Wolf2014-08-15
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* Added RTLIL::SigSpec::to_sigbit_map()Clifford Wolf2014-08-14
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* Changed the AST genWidthRTLIL subst interface to use a std::mapClifford Wolf2014-08-14
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* Fixed line numbers when using here-doc macrosClifford Wolf2014-08-14
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* Fixed handling of task outputsClifford Wolf2014-08-14
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* Added module->portsClifford Wolf2014-08-14
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* Added support for non-standard """ macro bodiesClifford Wolf2014-08-13
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* Fixed building verific bindingsClifford Wolf2014-08-12
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* Also allow "module foobar(input foo, output bar, ...);" syntaxClifford Wolf2014-08-07
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* Added AST_MULTIRANGE (arrays with more than 1 dimension)Clifford Wolf2014-08-06
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* Improved scope resolution of local regs in Verilog+AST frontendClifford Wolf2014-08-05
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* Fixed AST handling of variables declared inside a functions main blockClifford Wolf2014-08-05
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* Added support for non-standard "module mod_name(...);" syntaxClifford Wolf2014-08-04
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* More bugfixes related to new RTLIL::IdStringClifford Wolf2014-08-02
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* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-02
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* Preparations for RTLIL::IdString redesign: cleanup of existing codeClifford Wolf2014-08-02
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* Replaced sha1 implementationClifford Wolf2014-08-01
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* Fixed build of verific bindingsClifford Wolf2014-07-31
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* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-31
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* Added module->design and cell->module, wire->module pointersClifford Wolf2014-07-31
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* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-31
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* Fixed counting verilog line numbers for "// synopsys translate_off" sectionsClifford Wolf2014-07-30
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* Fixed Verilog pre-processor for files with no trailing newlineClifford Wolf2014-07-29
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* Added $shift and $shiftx cell types (needed for correct part select behavior)Clifford Wolf2014-07-29
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* Removed left over debug codeClifford Wolf2014-07-28
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* Fixed part selects of parametersClifford Wolf2014-07-28
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* Set results of out-of-bounds static bit/part select to undefClifford Wolf2014-07-28
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* Fixed RTLIL code generator for part select of parameterClifford Wolf2014-07-28
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* Fixed width detection for part selectsClifford Wolf2014-07-28
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* Added support for "upto" wires to Verilog front- and back-endClifford Wolf2014-07-28
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* Added wire->upto flag for signals such as "wire [0:7] x;"Clifford Wolf2014-07-28
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* Using log_assert() instead of assert()Clifford Wolf2014-07-28
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