yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	SystemVerilog also has assume(), added implicit -D FORMAL	Clifford Wolf	2015-10-13
*	Added support for "parameter" and "localparam" in global context	Clifford Wolf	2015-10-07
*	Fixed complexity of assigning to vectors in constant functions	Clifford Wolf	2015-10-01
*	Fixed detection of unconditional $readmem[hb]	Clifford Wolf	2015-09-30
*	Bugfixes in $readmem[hb]	Clifford Wolf	2015-09-25
*	Fixed segfault in AstNode::asReal	Clifford Wolf	2015-09-25
*	Added read-enable to memory model	Clifford Wolf	2015-09-25
*	Fixed AstNode::mkconst_bits() segfault on zero-sized constant	Clifford Wolf	2015-09-24
*	Added read_verilog -nodpi	Clifford Wolf	2015-09-23
*	Bugfix in handling of multi-dimensional memories	Clifford Wolf	2015-09-23
*	Warning for $display/$write outside initial block	Clifford Wolf	2015-09-23
*	Fixed support for $write system task	Clifford Wolf	2015-09-23
*	Fixed detection of "task foo(bar);" syntax error	Clifford Wolf	2015-09-22
*	Fixed multi-level prefix resolving	Clifford Wolf	2015-09-22
*	Fixed segfault on invalid verilog constant 1'b_	Clifford Wolf	2015-09-22
*	Improvements to $display system task	Andrew Zonenberg	2015-09-19
*	Added AST_INITIAL checks for $finish and $display	Clifford Wolf	2015-09-18
*	Initial implementation of $display()	Andrew Zonenberg	2015-09-18
*	Initial implementation of $finish()	Andrew Zonenberg	2015-09-18
*	gcc-4.6 build fixes	Clifford Wolf	2015-09-01
*	Fixed handling of memory read without address	Clifford Wolf	2015-08-22
*	Small corrections to const2ast warning messages	Clifford Wolf	2015-08-17
*	Check base-n literals only contain valid digits	Florian Zeitz	2015-08-17
*	Warn on literals exceeding the specified bit width	Florian Zeitz	2015-08-17
*	Another block of spelling fixes	Larry Doolittle	2015-08-14
*	Keep gcc from complaining about uninitialized variables	Larry Doolittle	2015-08-14
*	Re-created command-reference-manual.tex, copied some doc fixes to online help	Clifford Wolf	2015-08-14
*	Spell check (by Larry Doolittle)	Clifford Wolf	2015-08-14
*	Adjust makefiles to work with out-of-tree builds	Clifford Wolf	2015-08-12
*	Fixed handling of [a-fxz?] in decimal constants	Clifford Wolf	2015-08-11
*	Add -noautowire option to verilog frontend	Marcus Comstedt	2015-08-01
*	Added WORDS parameter to $meminit	Clifford Wolf	2015-07-31
*	Fixed nested mem2reg	Clifford Wolf	2015-07-29
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02
*	Fixed handling of parameters with reversed range	Clifford Wolf	2015-06-08
*	Fixed signedness of genvar expressions	Clifford Wolf	2015-05-29
*	Improvements in BLIF front-end	Clifford Wolf	2015-05-24
*	bugfix in blif front-end	Clifford Wolf	2015-05-18
*	Improved .latch support in BLIF front-end	Clifford Wolf	2015-05-17
*	Added read_blif command	Clifford Wolf	2015-05-17
*	Generalized blifparse API	Clifford Wolf	2015-05-17
*	abc/blifparse files reorganization	Clifford Wolf	2015-05-17
*	Verific build fixes	Clifford Wolf	2015-05-17
*	Verilog front-end: define `BLACKBOX in -lib mode	Clifford Wolf	2015-04-19
*	Ignore celldefine directive in verilog front-end	Clifford Wolf	2015-03-25
*	Const-fold parameter defs on-demand in AstNode::detectSignWidthWorker()	Clifford Wolf	2015-03-01
*	Added non-std verilog assume() statement	Clifford Wolf	2015-02-26
*	Added deep recursion warning to AST simplify	Clifford Wolf	2015-02-20
*	Parser support for complex delay expressions	Clifford Wolf	2015-02-20
*	YosysJS stuff	Clifford Wolf	2015-02-19