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* fixed Verilog parser filename and line numbering issue with include filesJohann Glaser2013-08-21
* Added support for include directories with the new '-I' argument of theJohann Glaser2013-08-20
* Added support for notif0/notif1 primitivesJohann Glaser2013-08-20
* Fixed width and sign detection for ** operatorClifford Wolf2013-08-19
* Added support for bufif0/bufif1 primitivesClifford Wolf2013-08-19
* Improved ast dumping (ast/verilog frontend)Clifford Wolf2013-08-19
* Added support for "2**n" shifter encodingClifford Wolf2013-08-12
* Added $div and $mod technology mappingClifford Wolf2013-08-09
* Added "design" command (-reset, -save, -load)Clifford Wolf2013-07-27
* More fixes in ternary op sign handlingClifford Wolf2013-07-12
* Fixed sign handling in ternary operatorClifford Wolf2013-07-12
* Another vloghammer related bugfixClifford Wolf2013-07-11
* Fixed sign propagation in bit-wise operatorsClifford Wolf2013-07-09
* More fixes in ast expression sign/width handlingClifford Wolf2013-07-09
* Major redesign of expr width/sign detecion (verilog/ast frontend)Clifford Wolf2013-07-09
* Fixed another bug found using vloghammerClifford Wolf2013-07-07
* Fixed AST_CONSTANT node generationClifford Wolf2013-07-07
* Added defparam support to Verilog/AST frontendClifford Wolf2013-07-04
* More fixes for bugs found using xsthammerClifford Wolf2013-06-13
* Further improved and extended xsthammerClifford Wolf2013-06-11
* Sign-extension related fixes in SatGen and AST frontendClifford Wolf2013-06-10
* Fixes and improvements in AST const foldingClifford Wolf2013-06-10
* Enabled AST/Verilog front-end optimizations per defaultClifford Wolf2013-06-10
* Added SAT generator and simple sat_solve commandClifford Wolf2013-06-07
* Added log_assert() apiClifford Wolf2013-05-24
* Fixed memory leak in ilang frontendClifford Wolf2013-05-23
* added option '-Dname[=definition]' to command 'read_verilog'Johann Glaser2013-05-19
* Merge branch 'bugfix'Clifford Wolf2013-05-16
| * Fixed synthesis of functions in latched blocksClifford Wolf2013-05-16
* | Added support for verilog === operatorClifford Wolf2013-05-07
* | Fixed handling of positional module parametersClifford Wolf2013-04-26
* | Only use sha1 checksums for names of parametric modules when the verbose form...Clifford Wolf2013-04-26
* | Fixed a bug in AST frontend for cases with non-blocking assigned variables as...Clifford Wolf2013-04-13
* | Now only use value from "initial" when no matching "always" block is foundClifford Wolf2013-03-31
* | Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)Clifford Wolf2013-03-31
* | Implemented proper handling of stub placeholder modulesClifford Wolf2013-03-28
* | Improvements and bugfixes for generate blocks with local signalsClifford Wolf2013-03-26
* | Fixed handling of unconditional generate blocksClifford Wolf2013-03-26
* Added nosync attribute and some async reset related fixesClifford Wolf2013-03-25
* Added mem2reg option to verilog frontendClifford Wolf2013-03-24
* Another fix in mem2reg ast simplify logicClifford Wolf2013-03-24
* Improved mem2reg handling in ast simplifierClifford Wolf2013-03-24
* Tiny fixes to verilog parserClifford Wolf2013-03-23
* Added help messages to ilang and verilog frontendsClifford Wolf2013-03-01
* Moved stand-alone libs to libs/ directory and added libs/subcircuitClifford Wolf2013-02-27
* Added support for verilog genblock[index].member syntaxClifford Wolf2013-02-26
* Added support for "always @(*)"Clifford Wolf2013-01-16
* added .gitignore filesClifford Wolf2013-01-05
* initial importClifford Wolf2013-01-05