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Author
Age
*
Replaced RTLIL::Const::str with generic decoder method
Clifford Wolf
2013-12-04
*
Added support for local regs in named blocks
Clifford Wolf
2013-12-04
*
Fixed temp net name generation in rtlil process generator for abbreviated nam...
Clifford Wolf
2013-11-28
*
Added "src" attribute to processes
Clifford Wolf
2013-11-28
*
Added module->avail_parameters (for advanced techmap features)
Clifford Wolf
2013-11-24
*
Added verilog frontend -ignore_redef option
Clifford Wolf
2013-11-24
*
Early wire/reg/parameter width calculation in ast/simplify
Clifford Wolf
2013-11-24
*
Added support for signed parameters in ilang
Clifford Wolf
2013-11-24
*
Remove auto_wire framework (smarter than the verilog standard)
Clifford Wolf
2013-11-24
*
Implemented correct handling of signed module parameters
Clifford Wolf
2013-11-24
*
Improved handling of initialized registers
Clifford Wolf
2013-11-23
*
Renamed "placeholder" to "blackbox"
Clifford Wolf
2013-11-22
*
Fixed O(n^2) performance bug in verilog preprocessor
Clifford Wolf
2013-11-22
*
Enable {* .. *} feature per default (removes dependency to REJECT feature in ...
Clifford Wolf
2013-11-22
*
Fixed async proc detection in mem2reg
Clifford Wolf
2013-11-21
*
Major improvements in mem2reg and added "init" sync rules
Clifford Wolf
2013-11-21
*
Fixed ilang parser: memory width
Clifford Wolf
2013-11-20
*
Another name resolution bugfix for generate blocks
Clifford Wolf
2013-11-20
*
Implemented indexed part selects
Clifford Wolf
2013-11-20
*
Do not allow memory bit select on the left side of an assignment
Clifford Wolf
2013-11-20
*
Added "synthesis" in (synopsys|synthesis) comment support
Clifford Wolf
2013-11-20
*
Fixed name resolution of local tasks and functions in generate block
Clifford Wolf
2013-11-20
*
Implemented part/bit select on memory read
Clifford Wolf
2013-11-20
*
Added init= attribute for fpga-style reset values
Clifford Wolf
2013-11-20
*
Fixed parsing of module arguments when one type is used for many args
Clifford Wolf
2013-11-19
*
Fixed two bugs in mem2reg functionality in AST frontend
Clifford Wolf
2013-11-18
*
Added dumping of attributes in AST frontend
Clifford Wolf
2013-11-18
*
Fixed parsing of default cases when not last case
Clifford Wolf
2013-11-18
*
Fixed mem2reg for reg usage outside always block
Clifford Wolf
2013-11-18
*
Fixed parsing of "parameter integer"
Clifford Wolf
2013-11-13
*
Cleanups and bugfixes in response to new internal cell checker
Clifford Wolf
2013-11-11
*
Call internal checker more often
Clifford Wolf
2013-11-10
*
More undef-propagation related fixes
Clifford Wolf
2013-11-08
*
Fixed handling of different signedness in power operands
Clifford Wolf
2013-11-08
*
Implemented const folding of ternary op with undef select
Clifford Wolf
2013-11-08
*
Fixed handling of power operator
Clifford Wolf
2013-11-07
*
Fixed more extend vs. extend_u0 issues
Clifford Wolf
2013-11-07
*
Disabled const folding of ternary op when select is undef
Clifford Wolf
2013-11-07
*
Renamed extend_un0() to extend_u0() and use it in genrtlil
Clifford Wolf
2013-11-07
*
Fixed sign handling in constants
Clifford Wolf
2013-11-07
*
Fixed const folding in corner cases with parameters
Clifford Wolf
2013-11-07
*
Fixed width detection for replicate operator
Clifford Wolf
2013-11-07
*
Fixed at_zero evaluation of dynamic ranges
Clifford Wolf
2013-11-07
*
Various fixes for correct parameter support
Clifford Wolf
2013-11-07
*
Fixed the fix for propagation of width hints for $signed() and $unsigned()
Clifford Wolf
2013-11-07
*
Fixed propagation of width hints for $signed() and $unsigned()
Clifford Wolf
2013-11-06
*
Additional fixes for undef propagation in concat and replicate ops
Clifford Wolf
2013-11-06
*
Improved width extension with regard to undef propagation
Clifford Wolf
2013-11-06
*
Another fix for early width and sign detection in ast simplifier
Clifford Wolf
2013-11-04
*
Fixed const folding of ternary operator
Clifford Wolf
2013-11-04
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