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Author
Age
*
AST simplifier: optimize constant AST_CASE nodes before recursively descending
Clifford Wolf
2014-10-29
*
Added support for task and function args in parentheses
Clifford Wolf
2014-10-27
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Improvements in $readmem[bh] implementation
Clifford Wolf
2014-10-26
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Added support for $readmemh/$readmemb
Clifford Wolf
2014-10-26
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Fixed constant "cond ? string1 : string2" with strings of different size
Clifford Wolf
2014-10-25
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Re-introduced Yosys::readsome() helper function
Clifford Wolf
2014-10-23
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minor indenting corrections
Clifford Wolf
2014-10-19
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Builds on Mac 10.9.2 with LLVM 3.5.
Parviz Palangpour
2014-10-19
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Fixed various VS warnings
Clifford Wolf
2014-10-18
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Header changes so it will compile on VS
William Speirs
2014-10-17
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Wrapped math in int constructor
William Speirs
2014-10-17
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Print "SystemVerilog" in "read_verilog -sv" log messages
Clifford Wolf
2014-10-16
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Fixed handling of invalid array access in mem2reg code
Clifford Wolf
2014-10-16
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Updated .gitignore file for ilang and verilog frontends
Clifford Wolf
2014-10-15
*
Replaced readsome() with read() and gcount()
Clifford Wolf
2014-10-15
*
Updated lexers & parsers to include prefixes
William Speirs
2014-10-15
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Added make_temp_{file,dir}() and remove_directory() APIs
Clifford Wolf
2014-10-12
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Added run_command() api to replace system() and popen()
Clifford Wolf
2014-10-12
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Do not the 'z' modifier in format string (another win32 fix)
Clifford Wolf
2014-10-11
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Fixed win32 troubles with f.readsome()
Clifford Wolf
2014-10-11
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Disabled vhdl2verilog command for win32 builds
Clifford Wolf
2014-10-11
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Added format __attribute__ to stringf()
Clifford Wolf
2014-10-10
*
Renamed SIZE() to GetSize() because of name collision on Win32
Clifford Wolf
2014-10-10
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namespace Yosys
Clifford Wolf
2014-09-27
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Another $clog2 bugfix
Clifford Wolf
2014-09-08
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Fixed $clog2 (off by one error)
Clifford Wolf
2014-09-06
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Fixed assignment of out-of bounds array element
Clifford Wolf
2014-09-06
*
Corrected spelling mistakes found by lintian
Ruben Undheim
2014-09-06
*
Removed $bu0 cell type
Clifford Wolf
2014-09-04
*
Removed compatbility.{h,cc}: Not using open_memstream/fmemopen anymore
Clifford Wolf
2014-08-23
*
Changed frontend-api from FILE to std::istream
Clifford Wolf
2014-08-23
*
Added emscripten (emcc) support to build system and some build fixes
Clifford Wolf
2014-08-22
*
Added support for non-standard <plugin>:<c_name> DPI syntax
Clifford Wolf
2014-08-22
*
Archibald Rust and Clifford Wolf: ffi-based dpi_call()
Clifford Wolf
2014-08-22
*
Fixed small memory leak in ast simplify
Clifford Wolf
2014-08-21
*
Added support for DPI function with different names in C and Verilog
Clifford Wolf
2014-08-21
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Added AstNode::asInt()
Clifford Wolf
2014-08-21
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Fixed memory leak in DPI function calls
Clifford Wolf
2014-08-21
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Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)
Clifford Wolf
2014-08-21
*
Added support for global tasks and functions
Clifford Wolf
2014-08-21
*
Added "via_celltype" attribute on task/func
Clifford Wolf
2014-08-18
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Added const folding of AST_CASE to AST simplifier
Clifford Wolf
2014-08-18
*
Improved AST ProcessGenerator performance
Clifford Wolf
2014-08-17
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Use stackmap<> in AST ProcessGenerator
Clifford Wolf
2014-08-17
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Added module->uniquify()
Clifford Wolf
2014-08-16
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AST ProcessGenerator: replaced subst_*_{from,to} with subst_*_map
Clifford Wolf
2014-08-16
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Renamed $_INV_ cell type to $_NOT_
Clifford Wolf
2014-08-15
*
Fixed bug in "read_verilog -ignore_redef"
Clifford Wolf
2014-08-15
*
Added RTLIL::SigSpec::to_sigbit_map()
Clifford Wolf
2014-08-14
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Changed the AST genWidthRTLIL subst interface to use a std::map
Clifford Wolf
2014-08-14
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