yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Fixed small memory leak in ast simplify	Clifford Wolf	2014-08-21
*	Added support for DPI function with different names in C and Verilog	Clifford Wolf	2014-08-21
*	Added AstNode::asInt()	Clifford Wolf	2014-08-21
*	Fixed memory leak in DPI function calls	Clifford Wolf	2014-08-21
*	Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)	Clifford Wolf	2014-08-21
*	Added support for global tasks and functions	Clifford Wolf	2014-08-21
*	Added "via_celltype" attribute on task/func	Clifford Wolf	2014-08-18
*	Added const folding of AST_CASE to AST simplifier	Clifford Wolf	2014-08-18
*	Improved AST ProcessGenerator performance	Clifford Wolf	2014-08-17
*	Use stackmap<> in AST ProcessGenerator	Clifford Wolf	2014-08-17
*	Added module->uniquify()	Clifford Wolf	2014-08-16
*	AST ProcessGenerator: replaced subst__{from,to} with subst__map	Clifford Wolf	2014-08-16
*	Renamed $_INV_ cell type to $_NOT_	Clifford Wolf	2014-08-15
*	Fixed bug in "read_verilog -ignore_redef"	Clifford Wolf	2014-08-15
*	Added RTLIL::SigSpec::to_sigbit_map()	Clifford Wolf	2014-08-14
*	Changed the AST genWidthRTLIL subst interface to use a std::map	Clifford Wolf	2014-08-14
*	Fixed line numbers when using here-doc macros	Clifford Wolf	2014-08-14
*	Fixed handling of task outputs	Clifford Wolf	2014-08-14
*	Added module->ports	Clifford Wolf	2014-08-14
*	Added support for non-standard """ macro bodies	Clifford Wolf	2014-08-13
*	Fixed building verific bindings	Clifford Wolf	2014-08-12
*	Also allow "module foobar(input foo, output bar, ...);" syntax	Clifford Wolf	2014-08-07
*	Added AST_MULTIRANGE (arrays with more than 1 dimension)	Clifford Wolf	2014-08-06
*	Improved scope resolution of local regs in Verilog+AST frontend	Clifford Wolf	2014-08-05
*	Fixed AST handling of variables declared inside a functions main block	Clifford Wolf	2014-08-05
*	Added support for non-standard "module mod_name(...);" syntax	Clifford Wolf	2014-08-04
*	More bugfixes related to new RTLIL::IdString	Clifford Wolf	2014-08-02
*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02
*	Preparations for RTLIL::IdString redesign: cleanup of existing code	Clifford Wolf	2014-08-02
*	Replaced sha1 implementation	Clifford Wolf	2014-08-01
*	Fixed build of verific bindings	Clifford Wolf	2014-07-31
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31
*	Added module->design and cell->module, wire->module pointers	Clifford Wolf	2014-07-31
*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31
*	Fixed counting verilog line numbers for "// synopsys translate_off" sections	Clifford Wolf	2014-07-30
*	Fixed Verilog pre-processor for files with no trailing newline	Clifford Wolf	2014-07-29
*	Added $shift and $shiftx cell types (needed for correct part select behavior)	Clifford Wolf	2014-07-29
*	Removed left over debug code	Clifford Wolf	2014-07-28
*	Fixed part selects of parameters	Clifford Wolf	2014-07-28
*	Set results of out-of-bounds static bit/part select to undef	Clifford Wolf	2014-07-28
*	Fixed RTLIL code generator for part select of parameter	Clifford Wolf	2014-07-28
*	Fixed width detection for part selects	Clifford Wolf	2014-07-28
*	Added support for "upto" wires to Verilog front- and back-end	Clifford Wolf	2014-07-28
*	Added wire->upto flag for signals such as "wire [0:7] x;"	Clifford Wolf	2014-07-28
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28
*	Fixed signdness detection of expressions with bit- and part-selects	Clifford Wolf	2014-07-28
*	Added proper Design->addModule interface	Clifford Wolf	2014-07-27
*	Fixed verific bindings for new RTLIL api	Clifford Wolf	2014-07-27
*	Fixed ilang parser for new RTLIL API	Clifford Wolf	2014-07-27
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27